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16 Commits

Author SHA1 Message Date
Wei Yan 45bcf9c6f2 clk: hix5hd2: add I2C clocks 
hix5hd2 add I2C clocks (I2C0~i2C5)

Signed-off-by: Wei Yan <sledge.yanwei@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
 2014-09-28 10:27:09 +08:00
Guoxiong Yan 1463fba39c clk: hix5hd2: add watchdog0 clocks 
hix5hd2 add watchdog0 clocks

Signed-off-by: Guoxiong Yan <yanguoxiong@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
 2014-09-28 10:27:04 +08:00
Jiancheng Xue cc855dd999 clk: hix5hd2: add sd clk 
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
 2014-09-28 10:27:01 +08:00
Zhangfei Gao 20e0755859 clk: hix5hd2: add complex clk 
Support clk of sata, usb and ethernet

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
 2014-09-28 10:26:49 +08:00
Zhangfei Gao 5efaf09021 clk: hisi: add clk-hix5hd2.c 
Signed-off-by: Haifeng Yan <haifeng.yan@linaro.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
 2014-05-12 11:30:32 +08:00
Zhangfei Gao 8b9dcb6cb7 clk: hisi: add hisi_clk_register_gate 
Add hisi_clk_register_gate register clk gate table

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
 2014-05-12 11:30:18 +08:00
Zhangfei Gao 156342a1e5 clk: hisi: use clk_register_mux_table in hisi_clk_register_mux 
Platform hix5hd2 use mux table, so use clk_register_mux_table instead

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
 2014-05-12 11:30:05 +08:00
Zhangfei Gao c115b13b85 clk: hisilicon: fix warning from smatch 
drivers/clk/hisilicon/clk-hi3620.c:338
mmc_clk_delay() warn: always true condition '(para >= 0) => (0-u32max >= 0)'

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2014-03-20 19:05:39 -07:00
Mike Turquette 7876114798 updating clock drivers for Hisilicon 
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Merge tag 'clk-hisi' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon

updating clock drivers for Hisilicon
 2014-03-19 12:54:03 -07:00
Haojian Zhuang 75af25f581 clk: hisi: remove static variable 
Remove the static variable. So these common clock register helper could
be used in more SoCs.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
 2014-03-19 15:31:27 +08:00
Haojian Zhuang d3e6573c48 clk: hip04: add clock driver 
Now only fixed rate clocks are appended into the clock driver.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
 2014-03-19 15:23:53 +08:00
Haojian Zhuang 16d1c8991c clk: hisi: assign missing clk to table 
The fixed rate and fixed factor clock isn't registered to clk table.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
 2014-03-19 15:23:32 +08:00
Zhangfei Gao 62ac983b61 clk: hisilicon: add hi3620_mmc_clks 
Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2014-02-26 16:03:56 -08:00
Haojian Zhuang ea010e5188 clk: hi3620: add gate clock flag 
Add missing CLK_SET_RATE_PARENT flag for gate clock.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
 2013-12-11 16:42:23 +08:00
Haojian Zhuang 5e39edd485 clk: hi3620: fix wrong flags on divider 
The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not
CLK_MUX_HIWORD_MASK.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
 2013-12-11 16:42:11 +08:00
Haojian Zhuang 0aa0c95f74 clk: hisilicon: add common clock support 
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
 2013-12-04 18:36:45 +08:00