Commit Graph

72 Commits

Author SHA1 Message Date
Paul Walmsley 657ebfadc1 OMAP3/4 clock: split into per-chip family files
clock34xx_data.c now contains data for the OMAP34xx family, the
OMAP36xx family, and the OMAP3517 family, so rename it to
clock3xxx_data.c.  Rename clock34xx.c to clock3xxx.c, and move the
chip family-specific clock functions to clock34xx.c, clock36xx.c, or
clock3517.c, as appropriate.  So now "clock3xxx.*" refers to the OMAP3
superset.

The main goal here is to prepare to compile chip family-specific clock
functions only for kernel builds that target that chip family.  To get to
that point, we also need to add CONFIG_SOC_* options for those other
chip families; that will be done in future patches, planned for 2.6.35.

OMAP4 is also affected by this.  It duplicated the OMAP3 non-CORE DPLL
clkops structure.  The OMAP4 variant of this clkops structure has been
removed, and since there was nothing else currently in clock44xx.c, it
too has been removed -- it can always be added back later when there
is some content for it.  (The OMAP4 clock autogeneration scripts have been
updated accordingly.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Ranjith Lohithakshan <ranjithl@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
2010-02-24 12:16:15 -07:00
Mike Turquette a7e069fc5a OMAP3630: Clock: Workaround for DPLL HS divider limitation
This patch implements a workaround for the DPLL HS divider limitation
in OMAP3630 as given by Errata ID: i556.

Errata:
When PWRDN bit is set, it resets the internal HSDIVIDER divide-by value (Mx).
The reset value gets loaded instead of the previous value.
The following HSDIVIDERs exhibit above behavior:
. DPLL4 : M6 / M5 / M4 / M3 / M2 (CM_CLKEN_PLL[31:26] register bits)
. DPLL3 : M3 (CM_CLKEN_PLL[12] register bit).

Work Around:
It is mandatory to apply the following sequence to ensure the write
value will
be loaded in DPLL HSDIVIDER FSM:
The global sequence when using PWRDN bit is the following:
. Disable Mx HSDIVIDER clock output related functional clock enable bits
        (in CM_FCLKEN_xxx / CM_ICLKEN_xxx)
. Enable PWRDN bit of HSDIVIDER
. Disable PWRDN bit of HSDIVIDER
. Read current HSDIVIDER register value
. Write different value in HSDIVIDER register
. Write expected value in HSDIVIDER register
. Enable Mx HSDIVIDER clock output related functional clocks
        (CM_FCLKEN_xxx / CM_ICLKEN_xxx)

Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Vijaykumar GN <vijaykumar.gn@ti.com>
[paul@pwsan.com: updated patch to apply; made workaround function static;
 marked as being 36xx-specific]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:06:00 -07:00
Sanjeev Premi a51ba28407 OMAP3 clock: Check return values for clk_get()
This patch checks if clk_get() returned success for
the clocks used in function omap2_clk_arch_init().

This version incorporates review comments from
Kevin Hilman and Paul Walmsley.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:56 -07:00
Ranjith Lohithakshan 3cc4a2fc2e AM35xx: Add clock support for new modules on AM35xx
This patch adds clock support for the following AM35xx modules
	- Ethernet MAC
	- CAN Controller (HECC)
	- New MUSB OTG Controller with integrated Phy
	- Video Processing Front End (VPFE)
	- Additional UART (UART4)

Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:55 -07:00
Ranjith Lohithakshan 419cc97d36 OMAP2/3 clock: Extend find_idlest() to pass back idle state value
Current implementation defines clock idle state indicators based on the
cpu information (cpu_is_omap24xx() or cpu_is_omap34xx()) in a system wide
manner. This patch extends the find_idlest() function in clkops to pass
back the idle state indicator for that clock, thus allowing idle state
indicators to be defined on a per clock basis if required.

This is specifically needed on AM35xx devices as the new IPSS clocks
indicates the idle status (0 is idle, 1 is ready) in a way just
opposite to how its handled in OMAP3 (0 is ready, 1 is idle).

Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
[paul@pwsan.com: updated to apply after commit 98c45457 et seq.]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-02-24 12:05:54 -07:00
Tony Lindgren 4751227df9 omap3/4: Fix compile for multi-omap for clkops_noncore_dpll_ops
Rename clkops_noncore_dpll_ops for omap3 and omap4.

Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-02-15 09:27:25 -08:00
Paul Walmsley e80a9729b1 OMAP2/3/4 clock: rename and clean the omap2_clk_init() functions
Rename the omap2_clk_init() in the OMAP2, 3, and 4 clock code to be
omap2xxx_clk_init(), omap3xxx_clk_init(), etc.  Remove all traces of
the (commented) old virt_prcm_set code from omap3xxx_clk_init() and
omap4xxx_clk_init(), since this will be handled with the OPP code that
is cooking in the PM branch.

After this patch, there should be very little else in the clock code
that blocks a multi-OMAP 2+3 kernel.  (OMAP2420+OMAP2430 still has some
outstanding issues that need to be resolved; this is pending on some
additions to the hwmod data.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-29 10:14:22 -07:00
Paul Walmsley feec1277a5 OMAP2/3/4 clock: omap2_clk_prepare_for_reboot() is OMAP2xxx-only
omap2_clk_prepare_for_reboot() is only applicable to OMAP2xxx chips,
so rename it to omap2xxx_clk_prepare_for_reboot() and only call it when
running on OMAP2xxx chips.  Remove the old stub in the OMAP3 clock code.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-29 10:14:22 -07:00
Paul Walmsley da4d2904ab OMAP2/3 clock: remove unnecessary includes and clean up header
Now that almost all of the code has been removed from clock2xxx.c and
clock34xx.c, many of the includes are now unnecessary and can be removed.
While we're here, standardize the initial comment blocks.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Jouni Högander <jouni.hogander@nokia.com>
2010-01-29 10:14:22 -07:00
Paul Walmsley 4680c29f69 OMAP2/3 clock: clean up omap*_clk_arch_init()
In the OMAP3xxx clock code, remove the #ifdef CONFIG_ARCH_OMAP3 in
clock34xx.c, since this file is only compiled for OMAP3xxx builds.  Also,
rename omap2_clk_arch_init in this file to omap3xxx_clk_arch_init() to
pave the way for multi-OMAP kernels.  Ensure that it is not executed
on non-OMAP3xxx systems.

In the OMAP2xxx clock code, rename omap2_clk_arch_init in this file to
omap2xxx_clk_arch_init() to pave the way for multi-OMAP kernels.
Ensure that it is not executed on non-OMAP2xxx systems.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-29 10:14:22 -07:00
Paul Walmsley 35e424e2c0 OMAP3 clock: split out DPLL3 M2 divider functions into mach-omap2/clkt34xx_dpll3m2.c
Split the DPLL3 M2 divider clock functions out of clock34xx.c and move
them into mach-omap2/clkt34xx_dpll3m2.c. This is intended to make the
clock code easier to understand, since all of the functions needed to
manage the OMAP3 DPLL3 M2 divider are now located in their own file,
rather than being mixed with other, unrelated functions.

Clock debugging is also now more finely-grained, since the DEBUG macro
can now be defined for the DPLL3 M2 clock alone.  This should reduce
unnecessary console noise when debugging DVFS.

Also, if at some future point the mach-omap2/ directory is split
into OMAP2/3/4 variants, this clkt file can be placed in the mach-omap34xx/
directory, rather than shared with other chip types that don't use this
clock type.

This patch also lays the groundwork to skip compilation of this
code on OMAP3 chips that don't support DVFS (e.g., AM35xx) via
the Makefile, rather than via #ifdefs.

Thanks to Alexander Shishkin <virtuoso@slind.org> for his comments to
improve the patch description.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jouni Högander <jouni.hogander@nokia.com>
Cc: Alexander Shishkin <virtuoso@slind.org>
2010-01-28 18:13:50 -07:00
Paul Walmsley 69ecefca51 OMAP2/3/4 clock: combine all omap2_clk_functions
The struct clk_functions for OMAP2, 3, and 4 are all essentially the
same, so combine them.  This removes one multi-OMAP kernel impediment
and saves memory on multi-OMAP builds.

The stubs for omap2_clk_{init,exit}_cpufreq() code will removed once
the OPP layer code that's currently in Kevin's PM branch is merged.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
2010-01-26 20:13:04 -07:00
Huang Weiyi 48bca0e9c7 OMAP2: remove duplicated #include
Remove duplicated #include('s) in
  arch/arm/mach-omap2/clock34xx.c
  arch/arm/mach-omap2/io.c

Signed-off-by: Huang Weiyi <weiyi.huang@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-01-08 15:23:03 -07:00
Rajendra Nayak a1391d2768 ARM: OMAP4: PM: Move DPLL control apis to dpll.c
This patch moves all the dpll control api's to a
common file dpll.c. This is in preperation of omap4
support wherein most of these api's can be reused.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
2009-12-11 17:00:46 -07:00
Paul Walmsley 82e9bd5885 OMAP3 clock: convert clock34xx.h to clock34xx_data.c
The OMAP3 clock code currently #includes a large .h file full of static
data structures.  Instead, define the data in a .c file.

Russell King <linux@arm.linux.org.uk> proposed this new arrangement:

    http://marc.info/?l=linux-omap&m=125967425908895&w=2

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Russell King <linux@arm.linux.org.uk>
2009-12-11 16:12:15 -07:00
Paul Walmsley 55d8a65308 OMAP2/3: move SDRC macros to mach-omap2/sdrc.h
clock34xx.c contains some macros which probably belong in mach-omap2/sdrc.h.
Move those macros to mach-omap2/sdrc.h.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-12-11 16:12:11 -07:00
Paul Walmsley ebd893ded2 OMAP1/2/3 clock: remove paranoid checks in preparation for clock{,2xxx,3xxx}_data.c
Some parts of the clock code took advantage of the fact that the statically
allocated clock tree was in clock{,24xx,34xx}.c's local namespace to do some
extra argument checks.  These are overzealous and are more difficult to
maintain when the clock tree is in a separate namespace, so, remove them.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-12-11 16:12:07 -07:00
Tomi Valkeinen dadd2bb931 OMAP: OMAPFB: add omapdss device
The upcoming new display subsystem driver is divided to two devices,
omapdss and omapfb, of which omapdss handles the actual hardware.

This patch adds a dummy omapdss platform device for the current omapfb
driver, which is then used to get the clocks. This will make it possible
for the current and the new display drivers to co-exist.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Acked-by: Tony Lindgren <tony@atomide.com>
2009-12-09 12:04:32 +02:00
Linus Torvalds 1c496784a0 Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (149 commits)
  arm: omap: Add omap3_defconfig
  AM35xx: Defconfig for AM3517 EVM board
  AM35xx: Add support for AM3517 EVM board
  omap: 3630sdp: defconfig creation
  omap: 3630sdp: introduce 3630 sdp board support
  omap3: Add defconfig for IGEP v2 board
  omap3: Add minimal IGEP v2 support
  omap3: Add CompuLab CM-T35 defconfig
  omap3: Add CompuLab CM-T35 board support
  omap3: rx51: Add wl1251 wlan driver support
  omap3: rx51: Add SDRAM init
  omap1: Add default kernel configuration for Herald
  omap1: Add board support and LCD for HTC Herald
  omap: zoom2: update defconfig for LL_DEBUG_NONE
  omap: zoom3: defconfig creation
  omap3: zoom: Introduce zoom3 board support
  omap3: zoom: Drop i2c-1 speed to 2400
  omap3: zoom: rename zoom2 name to generic zoom
  omap3: zoom: split board file for software reuse
  omap3evm: MIgrate to smsc911x ethernet driver
  ...

Fix trivial conflict (two unrelated config options added next to each
other) in arch/arm/mach-omap2/Makefile
2009-12-08 08:15:29 -08:00
Alexander Shishkin 183bd50f4f ARM: 5843/1: OMAP3: add AMBA devices for ETM and ETB
This enables on-chip tracing components found in omap3xxx.

Signed-off-by: Alexander Shishkin <virtuoso@slind.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-02 10:25:23 +00:00
Tony Lindgren a76df42a67 Merge 7xx-iosplit-plat-merge with omap-fixes
Merge branch '7xx-iosplit-plat-merge' into omap-for-linus
2009-11-22 10:08:43 -08:00
Rajendra Nayak 9346f48b26 omap3: clock: Fix the DPLL freqsel computations
Fix the freqsel value computation. Use n instead of (n+1)

The formula in the TRM uses a zero-based N, hence the (n+1); however
at this point in the clock34xx.c code, N is one-based.

Hayati Bayrakdar <h-bayrakdar@ti.com> and Nishanth Menon <nm@ti.com> helped
track down this bug.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: modified commit message]
Cc: Hayati Bayrakdar <h-bayrakdar@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-11-17 14:14:10 -08:00
Tony Lindgren ce491cf854 omap: headers: Move remaining headers from include/mach to include/plat
Move the remaining headers under plat-omap/include/mach
to plat-omap/include/plat. Also search and replace the
files using these headers to include using the right path.

This was done with:

#!/bin/bash
mach_dir_old="arch/arm/plat-omap/include/mach"
plat_dir_new="arch/arm/plat-omap/include/plat"
headers=$(cd $mach_dir_old && ls *.h)
omap_dirs="arch/arm/*omap*/ \
drivers/video/omap \
sound/soc/omap"
other_files="drivers/leds/leds-ams-delta.c \
drivers/mfd/menelaus.c \
drivers/mfd/twl4030-core.c \
drivers/mtd/nand/ams-delta.c"

for header in $headers; do
	old="#include <mach\/$header"
	new="#include <plat\/$header"
	for dir in $omap_dirs; do
		find $dir -type f -name \*.[chS] | \
			xargs sed -i "s/$old/$new/"
	done
	find drivers/ -type f -name \*omap*.[chS] | \
		xargs sed -i "s/$old/$new/"
	for file in $other_files; do
		sed -i "s/$old/$new/" $file
	done
done

for header in $(ls $mach_dir_old/*.h); do
	git mv $header $plat_dir_new/
done

Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-10-20 09:40:47 -07:00
Rajendra Nayak 7a66a39b85 omap: Lock DPLL5 at boot
Lock DPLL5 at 120MHz at boot. The USBHOST 120MHz f-clock and
USBTLL f-clock are the only users of this DPLL, and 120MHz is
is the only recommended rate for these clocks.

With this patch, the 60 MHz ULPI clock is generated correctly.

Tested on an OMAP3430 SDP.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-10-05 13:31:44 -07:00
Sanjeev Premi 11b66383aa OMAP3 clock: Fixed processing of bootarg 'mpurate'
The argument 'mpurate' had no effect on the MPU
frequency. This patch fixes the same.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-09-03 20:13:58 +03:00
Paul Walmsley 3c82e229f0 OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices.  These devices are both interconnect
initiators and targets.  Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:

    Clock usbhost_48m_fck didn't enable in 100000 tries

Two bugs are fixed by this patch.  First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond.  ES1 chips
should not wait for these clocks to enable.  So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.

Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks.  It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1].  Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.

This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].

In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.

Problem reported by Jarkko Nikula <jhnikula@gmail.com>:

    http://marc.info/?l=linux-omap&m=124306184903679&w=2

...

1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
   DSS case).

2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.

3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html


Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 20:10:36 -06:00
Jean Pihet 58cda884ec OMAP3 SDRC: add support for 2 SDRAM chip selects
Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2
SDRAM parts connected to the SDRC.

This patch adds the following:
- add a new argument of type omap_sdrc_params struct*
to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
- adapted the OMAP boards files to the new prototype of
omap2_init_common_hw
- add the SDRC 2nd CS registers offsets defines
- adapt the sram sleep code to configure the SDRC for the 2nd CS

Note: If the 2nd param to omap2_init_common_hw is NULL, then the
parameters are not programmed into the SDRC CS1 registers

Tested on 3430 SDP and Beagleboard rev C2 and B5, with
suspend/resume and frequency changes (cpufreq).

Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 19:43:25 -06:00
Tero Kristo 3afec6332e OMAP3: Add support for DPLL3 divisor values higher than 2
Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
2009-06-19 19:09:32 -06:00
Paul Walmsley d0ba3922ae OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency.  Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:31 -06:00
Paul Walmsley c9812d042a OMAP3 clock: add a short delay when lowering CORE clk rate
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize.  Without this delay, the system is prone to random
panics upon re-entering SDRAM.

This time delay varies based on MPU frequency.  At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:31 -06:00
Paul Walmsley 2f135eaf18 OMAP3 clock: initialize SDRC timings at kernel start
On the OMAP3, initialize SDRC timings when the kernel boots.  This ensures
that the kernel is running with known, optimized SDRC timings, rather than
whatever was configured by the bootloader.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:30 -06:00
Kevin Hilman 8111b221a2 OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM init
Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework
and ensure that auto-idle bits are set for these clocks during PRCM
init.

Also add omap3_d2d_idle() function called durint PRCM setup which
ensures D2D pins are MUX'd correctly to enable retention for
standalone (no-modem) devices.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-05-28 10:59:07 -07:00
Tony Lindgren 88b6f7eb9b Merge branch 'omap-clock-upstream' of git://git.pwsan.com/linux-2.6 into for-next 2009-05-26 14:41:35 -07:00
Tony Lindgren 005187eeca ARM: OMAP2/3: Change omapfb to use clkdev for dispc and rfbi, v2
This makes the framebuffer work on omap3.

Also fix the clk_get usage for checkpatch.pl
"ERROR: do not use assignment in if condition".

Cc: Imre Deak <imre.deak@nokia.com>
Cc: linux-fbdev-devel@lists.sourceforge.net
Acked-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-16 08:28:17 -07:00
Paul Walmsley 7971687094 OMAP2xxx clock: rename clk_init_one() to clk_preinit()
Rename clk_init_one() to clk_preinit() to distinguish its function
from clk_init() and the individual struct clk init functions.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-12 17:50:30 -06:00
Paul Walmsley b7aee4bfa7 OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code
The CORE DPLL M2 frequency change code should use pr_debug(), not
pr_info(), for its debug messages.  Same with
omap2_clksel_round_rate_div().  While here, convert a few printk(KERN_ERR ..
into pr_err().

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-12 17:27:10 -06:00
Paul Walmsley 4519c2bf43 OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz
According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
clock frequency from 83MHz to 166MHz.  CDP code unconditionally
unlocked the DLL whenever shifting to a lower SDRC speed, but this
seems unnecessary and error-prone, as the DLL is no longer able to
compensate for process, voltage, and temperature variations.  Instead,
only unlock the DLL when the SDRC clock rate would be less than 83MHz.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-12 17:27:10 -06:00
Tony Lindgren 4ea60b0c7a ARM: OMAP2/3: Add name for musb clocks
With the clkdev, musb_core.c needs to register clock with name "ick".

Once all the platforms using the musb driver have been converted
to use clockdev, the clock name does not need to be passed
from the low-level init code.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-05-12 11:20:30 -07:00
Russell King c0bf31320d [ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.

For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure.  Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled.  Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately.  Finally, we update the clock's parent, and then
disable the unused clocks.

This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL.  This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 17:28:30 +00:00
Russell King 8b9dbc16d4 [ARM] omap: arrange for clock recalc methods to return the rate
linux-omap source commit 33d000c99ee393fe2042f93e8422f94976d276ce
introduces a way to "dry run" clock changes before they're committed.
However, this involves putting logic to handle this into each and
every recalc function, and unfortunately due to the caching, led to
some bugs.

Solve both of issues by making the recalc methods always return the
clock rate for the clock, which the caller decides what to do with.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-14 09:59:21 +00:00
Paul Walmsley 883992bd8f [ARM] OMAP2/3 clock: don't tinker with hardirqs when they are supposed to be disabled
Clock rate change code executes inside a spinlock with hardirqs
disabled.  The only code that should be messing around with the
hardirq state should be the plat-omap/clock.c code.  In the
omap2_reprogram_dpllcore() case, this probably just wastes cycles, but
in the omap3_core_dpll_m2_set_rate() case, this is a nasty bug.

linux-omap source commit is b9b6208dadb5e0d8b290900a3ffa911673ca97ed.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-08 17:50:47 +00:00
Russell King 3f0a820c4c [ARM] omap: create a proper tree of clocks
Traditionally, we've tracked the parent/child relationships between
clk structures by setting the child's parent member to point at the
upstream clock.  As a result, when decending the tree, we have had
to scan all clocks to find the children.

Avoid this wasteful scanning by keeping a list of the clock's children.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-08 17:50:42 +00:00
Russell King b5088c0d90 [ARM] omap: clks: call recalc after any rate change
This implements the remainder of:
  OMAP clock: move rate recalc, propagation code up to plat-omap/clock.c
from Paul Walmsley which is not covered by the previous:
  [ARM] omap: move clock propagation into core omap clock code
  [ARM] omap: remove unnecessary calls to propagate_rate()
  [ARM] omap: move propagate_rate() calls into generic omap clock code
commits.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-08 17:50:41 +00:00
Paul Walmsley 7b0f89d7bb [ARM] OMAP2/3 clock: use standard set_rate fn in omap2_clk_arch_init()
Use the standard clk_set_rate() function in omap2_clk_arch_init()
rather than omap2_select_table_rate() -- this will ensure that clock
rates are recalculated and propagated correctly after those operations
are consolidated into clk_set_rate().

linux-omap source commit is 03c03330017eeb445b01957608ff5db49a7151b6.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-08 17:50:41 +00:00
Paul Walmsley 0eafd4725c [ARM] OMAP3 clock: add omap3_core_dpll_m2_set_rate()
Add the omap3_core_dpll_m2_set_rate() function to the OMAP3 clock code,
which calls into the SRAM function omap3_sram_configure_core_dpll() to
change the CORE DPLL M2 divider.  (SRAM code is necessary since rate changes
on clocks upstream from the SDRC can glitch SDRAM accesses.)

Use this function for the set_rate function pointer in the dpll3_m2_ck
struct clk.  With this function in place, PM/OPP code should be able to
alter SDRAM speed via code similar to:

      clk_set_rate(&dpll3_m2_ck, target_rate).

linux-omap source commit is 7f8b2b0f4fe52238c67d79dedcd2794dcef4dddd.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-08 17:50:40 +00:00
Paul Walmsley f8de9b2c45 [ARM] OMAP2 SDRC: move mach-omap2/memory.h into mach/sdrc.h
Move the contents of the arch/arm/mach-omap2/memory.h file to the
existing mach/sdrc.h file, and remove memory.h.  Modify files which
include memory.h to include asm/arch/sdrc.h instead.

linux-omap source commit is e7ae2d89921372fc4b9712a32cc401d645597807.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-08 17:50:38 +00:00
Paul Walmsley 416db864c1 [ARM] OMAP3 clock: disable DPLL autoidle while waiting for DPLL to lock
During _omap3_noncore_dpll_lock(), if a DPLL has no active downstream
clocks and DPLL autoidle is enabled, the DPLL may never lock, since it
will enter autoidle immediately.  To resolve this, disable DPLL
autoidle while locking the DPLL, and unconditionally wait for the DPLL
to lock.  This fixes some bugs where the kernel would hang when returning
from retention or return the wrong rate for the DPLL.

This patch is a collaboration with Peter de Schrijver
<peter.de-schrijver@nokia.com> and Kevin Hilman
<khilman@deeprootsystems.com>.

linux-omap source commit is 3b7de4be879f1f4f55ae59882a5cbd80f6dcf0f0.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Peter de Schrijver <peter.de-schrijver@nokia.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-08 17:50:35 +00:00
Paul Walmsley c1bd7aaf67 [ARM] OMAP3 clock: convert dpll_data.idlest_bit to idlest_mask
Convert struct dpll_data.idlest_bit field to idlest_mask.  Needed since
OMAP2 uses two bits for DPLL IDLEST rather than one.

While here, add the missing idlest_* fields for DPLL3.

linux-omap source commits are 25bab0f176b0a97be18a1b38153f266c3a155784
and b0f7fd17db2aaf8e6e9a2732ae3f4de0874db01c.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-08 17:50:33 +00:00
Paul Walmsley f0587b63c2 [ARM] OMAP3 clock: fix DPLL jitter correction and rate programming
Fix DPLL jitter correction programming.  Previously,
omap3_noncore_dpll_program() stored the FREQSEL jitter correction
parameter to the wrong register.  This caused jitter correction to be set
incorrectly and also caused the DPLL divider to be programmed incorrectly.

Also, fix DPLL divider programming.  An off-by-one error existed in
omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher
divider than intended.

linux-omap source commit is 5c0ec88a2145cdf2f2c9cc5fae49635c4c2476c7.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-08 17:50:32 +00:00
Sergio Aguirre 6c8fe0b954 [ARM] OMAP: Add CSI2 clock struct for handling it with clock API
Add CSI2 clock struct for handling it with clock API when TI PM is disabled.

linux-omap source commit is 8b20f4498928459276bd3366e3381ad595d23432.

Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-08 17:50:27 +00:00