Commit Graph

6 Commits

Author SHA1 Message Date
Krzysztof Adamski 6e17b41816 clk: sunxi: Add apb0 gates for H3
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).

Since this gates behave just like any Allwinner clock gate, add a generic
compatible that can be reused if we don't have any clock to protect.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
[Maxime: Removed the H3 compatible from the simple-gates driver, reworked
         the commit log a bit]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-25 11:30:32 -08:00
Vishnu Patekar 2d6f5f0cf6 clk: sunxi: Add apb0 gates for A83T
APB0 is part of PRCM, and is compatible with earlier SOCs.
apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
This patch adds support for APB0 gates for A83T.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-02 14:11:46 +01:00
Chen-Yu Tsai 6d3a47c291 clk: sunxi: Add DRAM gates support for sun4i-a10
The A10/A20 share the same set of DRAM clock gates, which controls
direct memory access for some peripherals.

On the A10, bit 15 controls the system's DRAM clock output (possibly
to the DRAM chips), which we need to keep on.

On the A20 this has been moved to the DRAM controller, becoming a no-op.
However it is still listed in the user manual, so add it anyway.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-07 09:58:17 +01:00
Chen-Yu Tsai bfcba2ed83 clk: sunxi: Add sun9i A80 apbs gates support
This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-01 12:15:47 +01:00
Maxime Ripard 7d6ddad659 clk: sunxi: Add A33 gates support
The A33 gates are different from the A23 ones, add a new hook to simple
gates to handle this clock

Reported-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-09-18 22:02:17 +02:00
Maxime Ripard ee38b2698a clk: sunxi: Add a simple gates driver
The gates were handled with a common piece of framework that was
registering all gates array, that was not using the CLK_OF_DECLARE logic,
and was not using clock-indices but some private masks that were pretty
much equivalent.

Move this code in a new driver that handles all the gates array and solves
both these issues.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
[sboyd@codeaurora.org: Include clk.h for consumer API usage]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-12 00:59:15 -07:00