Commit Graph

28 Commits

Author SHA1 Message Date
Axel Lin c9e3b2d8f7 pinctrl: sunxi: Fix off-by-one for valid offset range checking
The valid offset range should be 0 ... chip->ngpio - 1.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-30 10:37:36 +02:00
Linus Walleij 07b7eb9279 pinctrl: sunxi: drop lock on error path
I forgot to drop the lock for the return inside the loop
protected by the spinlock in the pin config routine when
merging in -rc7 in commit 6ad30ce046

Reported-by: Sherman Yin <syin@broadcom.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-30 09:57:27 +02:00
Linus Walleij 6ad30ce046 Linux 3.11-rc7
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Merge tag 'v3.11-rc7' into devel

Merged in this to avoid conflicts with the big locking fixes
from upstream.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Conflicts:
	drivers/pinctrl/pinctrl-sunxi.c
2013-08-29 09:46:30 +02:00
Sherman Yin 03b054e969 pinctrl: Pass all configs to driver on pin_config_set()
When setting pin configuration in the pinctrl framework, pin_config_set() or
pin_config_group_set() is called in a loop to set one configuration at a time
for the specified pin or group.

This patch 1) removes the loop and 2) changes the API to pass the whole pin
config array to the driver.  It is now up to the driver to loop through the
configs.  This allows the driver to potentially combine configs and reduce the
number of writes to pin config registers.

All c files changed have been build-tested to verify the change compiles and
that the corresponding .o is successfully generated.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28 13:34:41 +02:00
Maxime Ripard 23ac6df451 pinctrl: sunxi: Add Allwinner A20 pins set
The Allwinner A20 is pin-compatible with the older A10, so the two pin
set are quite similar. However, since the A20 has new features, we can't
just use the A10 pin set as is, and we need to define our own for the
A20.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:30 +02:00
Maxime Ripard de0c9029d5 pinctrl: sunxi: Add Allwinner A31 pins set
The Allwinner A31 SoC uses the same IP than the one found in the
A10/A13, with only different pins. Add the pins and the associated
functions found in the A31.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23 08:56:29 +02:00
Sachin Kamat 3efa921d5b pinctrl: sunxi: Fix incorrect NULL check
*map should be tested for NULL instead of map as kmalloc pointer
is assigned to it. This also fixes a potential null pointer dereference
bug later in the code.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07 22:29:39 +02:00
Maxime Ripard 1bee963db9 pinctrl: sunxi: Add spinlocks
The current code use no locking at all, which is obviously not that
great and can lead to concurrency issues, especially with the newer SMP
SoCs from Allwinner.

Add some locking where it's needed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2013-08-07 21:57:17 +02:00
Maxime Ripard df7b34f4c3 pinctrl: sunxi: Fix gpio_set behaviour
The current gpio_set function is ignoring the previous value set in the
GPIO value register, which leads in erasing the values already set for
the other GPIOs in the same bank when setting the value of a given GPIO.

Add the usual read/mask/write pattern to fix this brown paper bag bug.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2013-08-07 21:57:13 +02:00
Maxime Ripard 2aaaddff8d pinctrl: sunxi: Read register before writing to it in irq_set_type
The current irq_set_type code doesn't read the current register value
before writing to it, leading to the older programmed values being
overwritten and everything but the latest value being reset.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2013-08-07 20:39:25 +02:00
Maxime Ripard ac68936652 pinctrl: sunxi: Add Allwinner A10s pins
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-17 18:18:33 +02:00
Maxime Ripard 44abb933f7 pinctrl: sunxi: Move the pins definitions to a separate header
It will allow us to have a cleaner separation between the data needed by
the driver to work, and the core logic of the driver in itself, and will
allow having too much noise in the core driver in the future.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-17 18:18:32 +02:00
Maxime Ripard 7f884b6483 pinctrl: sunxi: Add external interrupt functions
The A10 and A13 has a few pins that can be muxed into a particular
function that can be used as an interrupt source. Add the available
pins for such functions to the A10 and A13 description array.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16 11:57:32 +02:00
Maxime Ripard 60242db1a7 pinctrl: sunxi: Add external interrupts support
The port controller IP found in the Allwinner A10 and A13 can use few of
the pins it manage as an interrupt source, called external interrupts in
the datasheet.

The number of these external interrupts are SoCs specific, but the
current upper limit is 32. In order to work, the external interrupts'
pins have to be muxed to a specific function to generate an interrupt.

This patch adds the irqchip and the needed logic to use the PIO
controller as an interrupt controller.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16 11:57:31 +02:00
Maxime Ripard 814d4f2e15 pinctrl: sunxi: Search the description array by pin id
Avoid to use expensive string manipulation functions and search by pin
id when possible.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16 11:56:53 +02:00
Wei Yongjun d72f88a42b pinctrl: sunxi: fix error return code in sunxi_pinctrl_probe()
Fix to return a negative error code from the devm_clk_get() error
handling case instead of 0, as done elsewhere in this function.

Introduced by commit 950707c0eb
(pinctrl: sunxi: add clock support)

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-27 15:37:09 +02:00
Axel Lin 97fc463769 pinctrl: Don't override the error code in probe error handling
Otherwise, we return 0 in probe error paths when gpiochip_remove() returns 0.
Also show error message if gpiochip_remove() fails.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-27 15:37:08 +02:00
Maxime Ripard cb51f8e8e3 pinctrl: sunxi: Rename wemac functions to emac
The pin functions associated to the ethernet controller were introduced
with the label "wemac", which was the name of the ethernet driver in the
allwinner source tree, while the real name of the IP is actually "emac",
as advertised in several documents including the datasheet.

Since this is part of the device tree bindings, and that these part of
the bindings have not yet be released in a kernel version, it seems like
the good timing to change it and assure consistency.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09 10:47:52 +02:00
Emilio López 950707c0eb pinctrl: sunxi: add clock support
For the port controller to work, we need to enable the apb0_pio gate.
This commit adds the ability to enable one clock specified on the device
tree to the pinctrl driver.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03 13:58:38 +02:00
Maxime Ripard ee341a99de pinctrl: sunxi: Add Allwinner A13 pin functions
The initial driver contained only a limited set of pins functions
because we lacked of documentation on it.

Now that we have such documentation, finish to fill the array.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07 09:05:14 +01:00
Maxime Ripard b5f50bf923 pinctrl: sunxi: Add Allwinner A10 pin functions
The initial driver contained only a limited set of pins functions
because we lacked of documentation on it.

Now that we have such documentation, finish to fill the array.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07 09:02:34 +01:00
Laurent Pinchart 022ab148d2 pinctrl: Declare operation structures as const
The pinconf, pinctrl and pinmux operation structures hold function
pointers that are never modified. Declare them as const.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07 05:27:29 +01:00
Maxime Ripard a0d72094f0 pinctrl: sunxi: add of_xlate function
Since the pin controller of sunxi chips is represented as a
single bank in the driver.

Since this is neither convenient nor represented that way in the
datasheets, define a custom of_xlate function with the layout
<bank pin flag>

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-05 17:32:29 +01:00
Maxime Ripard 9f5b6b30f9 ARM: pinctrl: sunxi: Add the pinctrl pin set for Allwinner A10
Since the Allwinner SoCs variants don't have the same set of pins to
handle, we need to declare the pin ranges available.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-01 10:45:34 +01:00
Maxime Ripard ae1575f711 pinctrl: sunxi: Document sun5i pins functions
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-01 10:44:21 +01:00
Maxime Ripard 08e9e614ca ARM: sunxi: gpio: Add Allwinner SoCs GPIO drivers
The IP responsible for the muxing on the Allwinner SoCs are also
handling the GPIOs on the system. This patch adds the needed driver that
relies on the pinctrl driver for most of its operations.

The number of pins available for GPIOs operations are already declared
in the pinctrl driver, we only need to probe a generic driver to handle
the banks available for each SoC.

This driver has been tested on a A13-Olinuxino.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-29 23:37:16 +01:00
Maxime Ripard eaa3d8489d ARM: pinctrl: sunxi: Add the pinctrl pin set for sun5i
Since the Allwinner SoCs variants don't have the same set of pins to
handle, we need to declare the pin ranges available.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22 13:51:35 +01:00
Maxime Ripard 0e37f88d9a ARM: sunxi: Add pinctrl driver for Allwinner SoCs
The Allwinner SoCs have an IP module that handle both the muxing and the
GPIOs.

This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC used on the board.

This driver only implements the pinctrl part, the gpio part will come
eventually.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22 13:51:15 +01:00