Commit Graph

21 Commits

Author SHA1 Message Date
Olof Johansson 84f1f0c199 bus: Add Tegra GMI support
This provides a driver to enable the use of the Generic Memory Interface
 found on Tegra SoCs that can host various types of high-speed devices.
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Merge tag 'tegra-for-4.10-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

bus: Add Tegra GMI support

This provides a driver to enable the use of the Generic Memory Interface
found on Tegra SoCs that can host various types of high-speed devices.

* tag 'tegra-for-4.10-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  bus: Add support for Tegra Generic Memory Interface
  dt/bindings: Add bindings for Tegra GMI controller

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-18 18:32:57 -08:00
Mirza Krak 40eb477678 bus: Add support for Tegra Generic Memory Interface
The Generic Memory Interface bus can be used to connect high-speed
devices such as NOR flash, FPGAs, DSPs...

Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: symmetry and coding style OCD]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-15 17:27:53 +01:00
Bartosz Golaszewski 8e7223fc86 bus: davinci: add support for da8xx bus master priority control
Create the driver for the da8xx master peripheral priority
configuration and implement support for writing to the three
Master Priority registers on da850 SoCs.

Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[nsekhar@ti.com: subject line adjustment]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2016-11-14 17:20:29 +05:30
Linus Walleij 335a127548 bus: qcom: add EBI2 driver
This adds a driver for the Qualcomm External Bus Interface EBI2
found in the MSM8660 and APQ8060 SoCs (at least).

This was tested with the SMSC9112 ethernet on the APQ8060
Dragonboard sitting on top of the SLOW CS2.

Some of my understanding if very vague and based on guesses and
extrapolations: the documentation in APQ8060 Qualcomm Application
Processor User Guide 80-N7150-14 Rev. A describes select features but
does not document the register bit fields.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-08 15:27:05 +02:00
Jon Hunter 46a88534af bus: Add support for Tegra ACONNECT
Add a bus driver for the Tegra ACONNECT which is used to interface to
various devices within the Audio Processing Engine (APE). The purpose
of the bus driver is to register child devices that are accessed via
the ACONNECT bus and through the device parent child relationship,
ensure that the appropriate power domain and clocks are enabled for
the ACONNECT when any of the child devices are active. Hence, the
ACONNECT driver simply enables runtime-pm for the ACONNECT device
so that when a child device is resumed, it will enable the power-domain
and clocks associated with the ACONNECT.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-01 16:35:43 +02:00
Masahiro Yamada 4b7f48d395 bus: uniphier-system-bus: add UniPhier System Bus driver
The UniPhier System Bus is an external bus that connects on-board
devices to the UniPhier SoC.  Each bank (chip select) is dynamically
mapped to the CPU-viewed address base via the bus controller.  The
bus controller must be configured before any access to the bus.

This driver parses the "ranges" property of the System Bus node and
initialized the bus controller.  After the bus becomes ready, devices
below it are populated.

Note:
Each bank can be mapped anywhere in the supported address space;
there is nothing preventing us from assigning bank 0 on 0x42000000,
0x43000000, or anywhere as long as such region is not used by others.
So, the "ranges" is just one possible software configuration, which
does not seem to fit in device tree because device tree is a hardware
description language.  However, of_translate_address() requires
"ranges" in every bus node between CPUs and device mapped on the CPU
address space.  In other words, "ranges" properties must be statically
defined in device tree.  After some discussion, I decided the dynamic
address reassignment by the driver is too bothersome.  Instead, the
device tree should provide a reasonable translation setup that the OS
can rely on.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
2015-12-22 11:22:39 -08:00
Chen-Yu Tsai d787dcdb9c bus: sunxi-rsb: Add driver for Allwinner Reduced Serial Bus
Reduced Serial Bus (RSB) is an Allwinner proprietery interface
used to communicate with PMICs and other peripheral ICs.

RSB is a two-wire push-pull serial bus that supports 1 master
device and up to 15 active slave devices.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-26 10:11:58 +09:00
Linus Torvalds 7d2b6ef19c ARM: SoC driver updates for v4.1
Driver updates for v4.1. Some of these are for drivers/soc, where we find more
 and more SoC-specific drivers these days. Some are for other driver subsystems
 where we have received acks from the appropriate maintainers.
 
 The larger parts of this branch are:
 
 - MediaTek support for their PMIC wrapper interface, a high-level interface
   for talking to the system PMIC over a dedicated I2C interface.
 - Qualcomm SCM driver has been moved to drivers/firmware. It's used for CPU
   up/down and needs to be in a shared location for arm/arm64 common code.
 - Cleanup of ARM-CCI PMU code.
 - Anoter set of cleanusp to the OMAP GPMC code.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for v4.1.  Some of these are for drivers/soc, where we
  find more and more SoC-specific drivers these days.  Some are for
  other driver subsystems where we have received acks from the
  appropriate maintainers.

  The larger parts of this branch are:

   - MediaTek support for their PMIC wrapper interface, a high-level
     interface for talking to the system PMIC over a dedicated I2C
     interface.

   - Qualcomm SCM driver has been moved to drivers/firmware.  It's used
     for CPU up/down and needs to be in a shared location for arm/arm64
     common code.

   - cleanup of ARM-CCI PMU code.

   - another set of cleanusp to the OMAP GPMC code"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits)
  soc/mediatek: Remove unused variables
  clocksource: atmel-st: select MFD_SYSCON
  soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs
  arm-cci: Fix CCI PMU event validation
  arm-cci: Split the code for PMU vs driver support
  arm-cci: Get rid of secure transactions for PMU driver
  arm-cci: Abstract the CCI400 PMU specific definitions
  arm-cci: Rearrange code for splitting PMU vs driver code
  drivers: cci: reject groups spanning multiple HW PMUs
  ARM: at91: remove useless include
  clocksource: atmel-st: remove mach/hardware dependency
  clocksource: atmel-st: use syscon/regmap
  ARM: at91: time: move the system timer driver to drivers/clocksource
  ARM: at91: properly initialize timer
  ARM: at91: at91rm9200: remove deprecated arm_pm_restart
  watchdog: at91rm9200: implement restart handler
  watchdog: at91rm9200: use the system timer syscon
  mfd: syscon: Add atmel system timer registers definition
  ARM: at91/dt: declare atmel,at91rm9200-st as a syscon
  soc: qcom: gsbi: Add support for ADM CRCI muxing
  ...
2015-04-22 09:18:17 -07:00
James Hogan 8286ae0330 MIPS: Add CDMM bus support
Add MIPS Common Device Memory Map (CDMM) support in the form of a bus in
the standard Linux device model. Each device attached via CDMM is
discoverable via an 8-bit type identifier and may contain a number of
blocks of memory mapped registers in the CDMM region. IRQs are expected
to be handled separately.

Due to the per-cpu (per-VPE for MT cores) nature of the CDMM devices,
all the driver callbacks take place from workqueues which are run on the
right CPU for the device in question, so that the driver doesn't need to
be as concerned about which CPU it is running on. Callbacks also exist
for when CPUs are taken offline, so that any per-CPU resources used by
the driver can be disabled so they don't get forcefully migrated. CDMM
devices are created as children of the CPU device they are attached to.

Any existing CDMM configuration by the bootloader will be inherited,
however platforms wishing to enable CDMM should implement the weak
mips_cdmm_phys_base() function (see asm/cdmm.h) so that the bus driver
knows where it should put the CDMM region in the physical address space
if the bootloader hasn't already enabled it.

A mips_cdmm_early_probe() function is also provided to allow early boot
or particularly low level code to set up the CDMM region and probe for a
specific device type, for example early console or KGDB IO drivers for
the EJTAG Fast Debug Channel (FDC) CDMM device.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9599/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-03-31 12:04:12 +02:00
Geert Uytterhoeven 89d463ea10 drivers: bus: Add Simple Power-Managed Bus Driver
Add a driver for transparent busses that don't need a real driver, but
where the bus controller is part of a PM domain, or under the control of
a functional clock.  Typically, the bus controller's PM domain and/or
clock must be enabled for child devices connected to the bus (either
on-SoC or externally) to function.

Hence the sole purpose of this driver is to enable its clock and PM
domain (if exist(s)), which are specified in the DT and managed from
platform and PM domain code, and to probe for child devices.

Due to the child-parent relationship with devices connected to the bus,
PM domain and clock state transitions are handled in the correct order.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-02-24 06:36:18 +09:00
Geert Uytterhoeven 6320c41198 drivers: bus: Sort Makefile entries alphabetically
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-02-24 06:36:16 +09:00
Pawel Moll a33b0daab7 bus: ARM CCN PMU driver
Driver providing perf backend for ARM Cache Coherent Network
interconnect. Supports counting all hardware events and crosspoint
watchpoints.

Currently works with CCN-504 only, although there should be
no changes required for CCN-508 (just impossible to test it now).

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-07-23 22:14:43 +02:00
Linus Torvalds a727eaf64f ARM: SoC driver changes
SoC-near driver changes that we're merging through our tree. Mostly
 because they depend on other changes we have staged, but in some cases
 because the driver maintainers preferred that we did it this way.
 
 This contains a largeish cleanup series of the omap_l3_noc bus driver,
 cpuidle rework for Exynos, some reset driver conversions and a long
 branch of TI EDMA fixes and cleanups, with more to come next release.
 
 The TI EDMA cleanups is a shared branch with the dmaengine tree, with
 a handful of Davinci-specific fixes on top.
 
 After discussion at last year's KS (and some more on the mailing lists),
 we are here adding a drivers/soc directory. The purpose of this is
 to keep per-vendor shared code that's needed by different drivers but
 that doesn't fit into the MFD (nor drivers/platform) model. We expect
 to keep merging contents for this hierarchy through arm-soc so we can
 keep an eye on what the vendors keep adding here and not making it a
 free-for-all to shove in crazy stuff.
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Merge tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next

Pull ARM SoC driver changes from Olof Johansson:
 "SoC-near driver changes that we're merging through our tree.  Mostly
  because they depend on other changes we have staged, but in some cases
  because the driver maintainers preferred that we did it this way.

  This contains a largeish cleanup series of the omap_l3_noc bus driver,
  cpuidle rework for Exynos, some reset driver conversions and a long
  branch of TI EDMA fixes and cleanups, with more to come next release.

  The TI EDMA cleanups is a shared branch with the dmaengine tree, with
  a handful of Davinci-specific fixes on top.

  After discussion at last year's KS (and some more on the mailing
  lists), we are here adding a drivers/soc directory.  The purpose of
  this is to keep per-vendor shared code that's needed by different
  drivers but that doesn't fit into the MFD (nor drivers/platform)
  model.  We expect to keep merging contents for this hierarchy through
  arm-soc so we can keep an eye on what the vendors keep adding here and
  not making it a free-for-all to shove in crazy stuff"

* tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits)
  cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
  tty: serial: msm: Remove direct access to GSBI
  power: reset: keystone-reset: introduce keystone reset driver
  Documentation: dt: add bindings for keystone pll control controller
  Documentation: dt: add bindings for keystone reset driver
  soc: qcom: fix of_device_id table
  ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos
  ARM: EXYNOS: Move the driver to drivers/cpuidle directory
  ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c
  ARM: EXYNOS: Pass the AFTR callback to the platform_data
  ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c
  ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier
  ARM: EXYNOS: Move the AFTR state function into pm.c
  ARM: EXYNOS: Encapsulate the AFTR code into a function
  ARM: EXYNOS: Disable cpuidle for exynos5440
  ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle
  ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle
  ARM: EXYNOS: Remove ifdef for scu_enable in pm
  ARM: EXYNOS: Move scu_enable in the cpu_pm notifier
  ARM: EXYNOS: Use the cpu_pm notifier for pm
  ...
2014-06-02 16:35:49 -07:00
Florian Fainelli 44127b771d bus: add Broadcom GISB bus arbiter timeout/error handler
This patch adds support for the Broadcom GISB arbiter bus timeout/error
handler. GISB is a proprietary bus used by Broadcom Set Top Box
System-on-a-chip devices (BCM7xxx) which allows multiple masters and
clients to be interfaced with each other.

The bus arbiter offers support for generating two interrupts towards the
host CPU, thus allowing us to "catch" clock gated masters, or masters
being volontarily blocked for powersaving purposes, or do general system
troubleshooting.

We also register a hook with the ARM fault exception handling to allow
printing a more informative message than "imprecise external abort at
0x00000000" for instance.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-05-24 00:58:39 +02:00
Pawel Moll 3b9334ac83 mfd: vexpress: Convert custom func API to regmap
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).

Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:

* a rework (and move to drivers/bus directory, as suggested
  by Samuel and Arnd) of the config bus core, which is much
  simpler now and uses device model infrastructure (class)
  to keep track of the bridges; non-DT case (soon to be
  retired anyway) is simply covered by a special device
  registration function

* the new config-bus driver also takes over device population,
  so there is no need for special matching table for
  of_platform_populate nor "simple-bus" hack in the arm64
  model dtsi file (relevant bindings documentation has
  been updated); this allows all the vexpress devices
  fit into normal device model, making it possible
  to remove plenty of early inits and other hacks in
  the near future

* adaptation of the syscfg bridge implementation in the
  sysreg driver, again making it much simpler; there is
  a special case of the "energy" function spanning two
  registers, where they should be both defined in the tree
  now, but backward compatibility is maintained in the code

* modification of the relevant drivers:

  * hwmon - just a straight-forward API change
  * power/reset driver - API change
  * regulator - API change plus error handling
    simplification
  * osc clock driver - this one required larger rework
    in order to turn in into a standard platform driver

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mike Turquette <mturquette@linaro.org>
2014-05-15 17:02:18 +01:00
Linus Torvalds ee1a8d402e ARM SoC device tree changes
These changes from 30 individual branches for the most part update device
 tree files, but there are also a few source code changes that have crept
 in this time, usually in order to atomically move over a driver from
 using hardcoded data to DT probing.
 
 A number of platforms change their DT files to use the C preprocessor,
 which is causing a bit of churn, but that is hopefully only this once.
 
 There are a few conflicts with the other branches unfortunately:
 
 * in exynos5440.dtsi and kirkwood-6281.dtsi, device nodes are added
   from multiple branches. Need to be careful to have the right
   set of closing braces as git gets this one wrong.
 
 * In kirkwood.dtsi, one 'ranges' line got split into two lines, while
   another line got added. Order of the lines does not matter.
 
 * in sama5d3.dtsi, some cleanup was merged the wrong way, causing
   a bogus conflict. We want the 'dmas' and 'dma-names' properties
   to get added here.
 
 * Two lines got removed independently in arch/arm/mach-mxs/mach-mxs.c
 
 * Contents get added independently in arch/arm/mach-omap2/cclock33xx_data.c
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree changes from Arnd Bergmann:
 "These changes from 30 individual branches for the most part update
  device tree files, but there are also a few source code changes that
  have crept in this time, usually in order to atomically move over a
  driver from using hardcoded data to DT probing.

  A number of platforms change their DT files to use the C preprocessor,
  which is causing a bit of churn, but that is hopefully only this once"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits)
  ARM: at91: dt: rm9200ek: add spi support
  ARM: at91: dt: rm9200: add spi support
  ARM: at91/DT: at91sam9n12: add SPI DMA client infos
  ARM: at91/DT: sama5d3: add SPI DMA client infos
  ARM: at91/DT: fix SPI compatibility string
  ARM: Kirkwood: Fix the internal register ranges translation
  ARM: dts: bcm281xx: change comment to C89 style
  ARM: mmc: bcm281xx SDHCI driver (dt mods)
  ARM: nomadik: add the new clocks to the device tree
  clk: nomadik: implement the Nomadik clocks properly
  ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency
  ARM: dts: omap4-panda: Fix DVI EDID reads
  ARM: dts: omap4-panda: Add USB Host support
  arm: mvebu: enable mini-PCIe connectors on Armada 370 RD
  ARM: shmobile: irqpin: add a DT property to enable masking on parent
  ARM: dts: AM43x EPOS EVM support
  ARM: dts: OMAP5: Add bandgap DT entry
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
  ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
  ...
2013-07-02 14:23:01 -07:00
Huang Shijie 85bf6d4e4b drivers: bus: add a new driver for WEIM
The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.

In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.

This patch also adds the devicetree binding document.
The driver only works when the devicetree is enabled.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 16:04:28 +08:00
Lorenzo Pieralisi ed69bdd8fd drivers: bus: add ARM CCI support
On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to it.

This patch enables the basic infrastructure required in Linux to handle and
programme the CCI component.

Non-local variables used by the CCI management functions called by power
down function calls after disabling the cache must be flushed out to main
memory in advance, otherwise incoherency of those values may occur if they
are sitting in the cache of some other CPU when power down functions
execute. Driver code ensures that relevant data structures are flushed
from inner and outer caches after the driver probe is completed.

CCI slave port resources are linked to set of CPUs through bus masters
phandle properties that link the interface resources to masters node in
the device tree.

Documentation describing the CCI DT bindings is provided with the patch.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2013-05-29 15:50:34 -04:00
Thomas Petazzoni fddddb52a6 bus: introduce an Marvell EBU MBus driver
The Marvell EBU SoCs have a configurable physical address space
layout: the physical ranges of memory used to address PCI(e)
interfaces, NOR flashes, SRAM and various other types of memory are
configurable by software, through a mechanism of so-called 'address
decoding windows'.

This new driver mvebu-mbus consolidates the existing code to address
the configuration of these memory ranges, which is spread into
mach-mvebu, mach-orion5x, mach-mv78xx0, mach-dove and mach-kirkwood.

Following patches convert each Marvell EBU SoC family to use this
driver, therefore removing the old code that was configuring the
address decoding windows.

It is worth mentioning that the MVEBU_MBUS Kconfig option is
intentionally added as a blind option. The new driver implements and
exports the mv_mbus_dram_info() function, which is used by various
Marvell drivers throughout the tree to get access to window
configuration parameters that they require. This function is also
implemented in arch/arm/plat-orion/addr-map.c, which ultimately gets
removed at the end of this patch series. So, in order to preserve
bisectability, we want to ensure that *either* this new driver, *or*
the legacy code in plat-orion/addr-map.c gets compiled in.

By making MVEBU_MBUS a blind option, we are sure that only a platform
that does 'select MVEBU_MBUS' will get this new driver compiled
in. Therefore, throughout the next patches that convert the Marvell
sub-architectures one after the other to this new driver, we add the
'select MVEBU_MBUS' and also ensure to remove plat-orion/addr-map.c
from the build for this specific sub-architecture. This ensures that
bisectability is preserved.

Ealier versions of this driver had a DT binding, but since those were
not yet agreed upon, they were removed. The driver still uses
of_device_id to find the SoC specific details according to the string
passed to mvebu_mbus_init(). The plan is to re-introduce a proper DT
binding as a followup set of patches.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-03-28 19:04:16 +00:00
Santosh Shilimkar 0ee7261c92 drivers: bus: Move the OMAP interconnect driver to drivers/bus/
OMAP interconnect drivers are used for the interconnect error handling.
Since they are bus driver, lets move it to newly created drivers/bus.

Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-09-19 16:53:26 +02:00
Kishon Vijay Abraham I 26a84b3eae drivers: bus: add a new driver for omap-ocp2scp
Adds a new driver *omap-ocp2scp*. This driver takes the responsibility of
creating all the devices that is connected to OCP2SCP. In the case of OMAP4,
USB2PHY is connected to ocp2scp.

This also includes device tree support for ocp2scp driver and
the documentation with device tree binding information is updated.

Acked-by: Felipe Balbi <balbi@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-08-22 14:31:49 +02:00