Commit Graph

16 Commits

Author SHA1 Message Date
Ben Skeggs 8b5f4d0def drm/nv50/pm: stabilise transition to 100MHz mclk a bit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:29 +10:00
Ben Skeggs 973e861657 drm/nv50/pm: avoid touching dom6/vdec clocks if perflvl doesn't define it
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:28 +10:00
Ben Skeggs 463464eb9b drm/nv50/pm: fix thinko which lead to clocks being slightly off sometimes
read_pll_ref() needs to take into account the refclk src bits in 0xc040 on
some chipsets, it wasn't doing this.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:27 +10:00
Ben Skeggs 6805979fa9 drm/nv50/pm: 0x84/0x86 can't use "1" for nvclk src, need 0x50 method
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:27 +10:00
Ben Skeggs 19fa224f8a drm/nv50/pm: free state struct after setting clocks
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:26 +10:00
Ben Skeggs f3fbaf34e2 drm/nv50/pm: rewrite clock management, and switch to the new pm hooks
This area is horrifically complicated on these chipsets, and it's likely we
will need at least a few more tweaks yet.

Oh yes, and it's completely disabled on IGPs for the moment.  From traces,
things look potentially different there yet again.  Sigh...

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:24 +10:00
Ben Skeggs 5a4267ab14 drm/nv50/pm: convert to new fanspeed pwm controller hooks
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:12 +10:00
Ben Skeggs 3f8e11e4b6 drm/nv50/pm: mostly nailed down fan pwm frequency selection
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:11 +10:00
Ben Skeggs cb9fa62671 drm/nv50/pm: add support for pwm fan control
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21 19:01:11 +10:00
Ben Skeggs 02e4f5877d drm/nouveau/bios: allow passing in crtc to the init table parser
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20 16:05:48 +10:00
Emil Velikov 619d4f7e21 drm/nv50: improve nv50_pm_get_clock()
Many of the nv50 cards have their shader and/or memory pll
disabled at some stage.
This patch addresses those cases, so that the function
returns the correct frequency.

When the shader pll is disabled, the blob reports 2*core clock
Whereas for memory, the data stored in the vbios. This action
is incorrect as some vbioses store a clock value that is less
than the refference clock of the pll.

Thus we are reporting the reff_clk as it is the frequency the
pll actually operates

v2 - Convert NV_INFO() messages to NV_DEBUG()
Provide more information in the actuall message

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:41 +10:00
Ben Skeggs fade7ad56d drm/nva3: split pm backend out from nv50
This will end up quite different, it makes sense for it to be completely
separate.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05 09:57:54 +10:00
Ben Skeggs aee582de80 drm/nouveau: run perflvl and M table scripts on mem clock change
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05 09:57:49 +10:00
Ben Skeggs 5c6dc65754 drm/nouveau: pass perflvl struct to clock_pre()
On certain boards, there's BIOS scripts and memory timings that need to
be modified with the memclk.  Just pass in the entire perflvl struct and
let the chipset-specific code decide what to do.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05 09:57:41 +10:00
Ben Skeggs 6f876986be drm/nouveau: allow static performance level setting
Guarded by a module parameter for the moment, read the code for the
magic value which enables it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24 16:27:20 +10:00
Ben Skeggs 02c30ca0a1 drm/nv50: import initial clock get/set routines + hook up pm engine
This will make nouveau_pm attempt to report the card's current performance
level both during bootup, and through sysfs.

This is a very initial implementation, and can be improved a *lot*

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24 16:27:06 +10:00