Commit Graph

1 Commits

Author SHA1 Message Date
Thierry Reding 02b0cc52c0 memory: tegra: Add Tegra186 support
The memory controller found on Tegra186 is different in some respects to
its predecessors. Most notably it no longer implements an SMMU, but does
assign ARM SMMU stream IDs for each memory client instead.

Provide a driver that programs these registers so that memory clients
can translate addresses via the ARM SMMU.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 12:58:21 +01:00