Commit Graph

14 Commits

Author SHA1 Message Date
Stephen Boyd a444723569 clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0
Failure to initialize this flag to 0 by default can result in
stack junk filling the clk_init_data structure and weird things
happen. Joachim noticed that the critical clk feature started
triggering for these clks causing boot failures, when it really
shouldn't have happened:

BUG: scheduling while atomic: swapper/0/0x00000002
CPU: 0 PID: 0 Comm: swapper Not tainted
4.6.0-rc6-next-20160505-00001-g5c8320450d1c #826
Hardware name: NXP LPC18xx/43xx (Device Tree)
[<2800be81>] (unwind_backtrace) from [<2800b22f>] (show_stack+0xb/0xc)
[<2800b22f>] (show_stack) from [<2801ea21>] (__schedule_bug+0x2d/0x44)
[<2801ea21>] (__schedule_bug) from [<281dc937>] (__schedule+0x3b/0x268)
[<281dc937>] (__schedule) from [<281dcbbb>] (schedule+0x57/0x64)
[<281dcbbb>] (schedule) from [<281de8ef>] (schedule_timeout+0xfb/0x120)
[<281de8ef>] (schedule_timeout) from [<28030fcd>] (msleep+0xf/0x12)
[<28030fcd>] (msleep) from [<28165a6d>] (clk_creg_32k_prepare+0x1f/0x24)
[<28165a6d>] (clk_creg_32k_prepare) from [<281620d5>]
(clk_core_prepare+0x1d/0x36)
[<281620d5>] (clk_core_prepare) from [<2816340b>] (clk_register+0x22f/0x318)
[<2816340b>] (clk_register) from [<282b06c9>] (lpc18xx_creg_clk_init+0x55/0x84)
[<282b06c9>] (lpc18xx_creg_clk_init) from [<282b0149>] (of_clk_init+0xc1/0x12c)
[<282b0149>] (of_clk_init) from [<282a665d>] (time_init+0x15/0x20)
[<282a665d>] (time_init) from [<282a457d>] (start_kernel+0x169/0x274)
[<282a457d>] (start_kernel) from [<28008025>] (0x28008025)
bad: scheduling from the idle thread!
CPU: 0 PID: 0 Comm: swapper Tainted: G W
4.6.0-rc6-next-20160505-00001-g5c8320450d1c #826

Fix this by initializing the flags member to 0.

Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06 10:55:11 -07:00
Joachim Eastwood 378523d150 clk: add lpc18xx creg clk driver
The CREG block on lpc18xx contains configuration register
for two low power clocks. Support enabling of these two
clocks with a clk driver that access CREG trough the
syscon regmap interface.

These clocks are needed to support peripherals like the
internal RTC on lpc18xx.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-04 12:52:10 -08:00
Sylvain Lemieux 8626556f25 clk: lpc32xx: fix compilation warning
Remove the following false positives compilation warning:
- drivers/clk/nxp/clk-lpc32xx.c: In function 'lpc32xx_clk_register':
  warning: 'hw' may be used uninitialized in this function [-Wmaybe-uninitialized]
- drivers/clk/nxp/clk-lpc32xx.c: In function 'clk_hclk_pll_round_rate':
  warning: 'p' may be used uninitialized in this function [-Wmaybe-uninitialized]
  warning: 'n' may be used uninitialized in this function [-Wmaybe-uninitialized]
  warning: 'm' may be used uninitialized in this function [-Wmaybe-uninitialized]

Tested using gcc version 4.7.3.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
[sboyd@codeaurora.org: Drop assignment of hw to NULL as return
silences it and is less likely to lead to hiding problems later]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:41:43 -08:00
Stephen Boyd 615b34de1f clk: nxp: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:45:22 -08:00
Sylvain Lemieux 7e0810c948 clk: lpc32xx: add HCLK PLL output configuration
This patch add the support to setup the HCLK PLL output
using the "assigned-clock-rates" parameter in the device tree.

If the option is not use, the clock setup by the kickstart
and/or bootloader remain unchanged.

The previous kernel version did not change the clock frequency
output setup by the kickstart and/or bootloader;
this version always setup the clock frequency output to 208MHz.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10 12:45:16 -08:00
Sylvain Lemieux 4db9a9ba60 clk: lpc32xx: do not register clock "0"
The following errors are display in the console during the power-on:
[    0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12
[    0.000000] lpc32xx_clk_init: failed to register (null) clock: -12

There is no need to register clock "0"; the first clock used is 1;

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
[sboyd@codeaurora.org: s/prepare/register/]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09 16:19:34 -08:00
Geliang Tang 5fd9c05c84 clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h
to_clk_*(_hw) macros have been repeatedly defined in many places.
This patch moves all the to_clk_*(_hw) definitions in the common
clock framework to public header clk-provider.h, and drop the local
definitions.

Signed-off-by: Geliang Tang <geliangtang@163.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:59:50 -08:00
Heiko Stuebner 5035981979 clk-divider: make sure read-only dividers do not write to their register
Commit e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.

On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.

To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.

The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.

Fixes: e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:44:37 -08:00
Vladimir Zapolskiy f7c82a60ba clk: lpc32xx: add common clock framework driver
Add support for all configurable clocks found on NXP LPC32xx SoC.

The list contains several heterogenous groups of clocks:
* system clocks including multiple dividers and muxes,
* x397 PLL, HCLK PLL and USB PLL,
* peripheral clocks inherited from rtc, hclk and pclk,
* USB controller clocks: AHB slave, I2C, OTG, OHCI and device.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24 12:31:26 -08:00
Joachim Eastwood c23a584769 clk: lpc18xx-cgu: fix potential system hang when disabling unused clocks
The clock consumer (CCU) of the CGU must be able to check if a CGU
base clock is really running since access to the CCU registers
requires a running base clock. Access with a disabled base clock will
cause the system to hang. Fix this issue by adding code that check if
the parent clock is running in the is_enabled clk_ops callback. Since
certain clocks can be cascaded this must be added to all clock gates.

The hang would occur if the boot ROM or boot loader didn't setup and
enable the USB0 clock. Then when the clk framework tried to access
the CCU register it would hang the system.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-26 12:36:58 -07:00
Joachim Eastwood 2a9a06f98f clk: lpc18xx-ccu: fix potential system hang when disabling unused clocks
CCU branch clock register must only be accessed while the base
(parent) clock is running. Access with a disabled base clock
will cause the system to hang. Fix this issue by adding code
that check if the parent clock is running in the is_enabled
clk_ops callback.

This hang would occur when disabling unused clocks after AMBA
runtime pm had already disabled some of the clocks.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-26 12:36:56 -07:00
Stephen Boyd 39482a1331 clk: nxp: Remove clk.h include
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Remove the include here because this is a
provider driver.

Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20 11:11:08 -07:00
Joachim Eastwood 472cd304a3 clk: add lpc18xx ccu clk driver
Add driver for NXP LPC18xx/43xx Clock Control Unit (CCU). The CCU
provides fine grained gating of most clocks present in the SoC.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-06-18 15:44:48 -07:00
Joachim Eastwood b04e0b8fd5 clk: add lpc18xx cgu clk driver
Add driver for NXP LPC18xx/43xx Clock Generation Unit (CGU). The CGU
contains several clock generators and output stages that route the
clocks either directly to peripherals or to a Clock Control Unit
(CCU).

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-06-18 15:44:47 -07:00