Commit Graph

30 Commits

Author SHA1 Message Date
Dinh Nguyen 56713da3ee clk: socfpga: allow for multiple parents on Arria10 periph clocks
There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.

Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22 14:17:37 -08:00
Arnd Bergmann 60ea57a433 clk: socfpga: fix __init annotation
clang found a bug with the __socfpga_pll_init definition:

drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and
      global variables

This moves the __init annotation to the right place so the function
actually gets discarded.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 14:13:31 -08:00
Dinh Nguyen 34d5003bfb clk: socfpga: Add a second parent option for the dbg_base_clk
The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.

This patch adds the option to get the correct parent for the debug base
clock.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:03 -07:00
Andy Shevchenko 25d4d341d3 clk: socfpga: switch to GENMASK()
Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:59:16 -07:00
Stephen Boyd b0af24b523 clk: socfpga: Remove clk.h and clkdev.h includes
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Remove the include here because this is a
provider driver. The clkdev.h include isn't used either, remove
it and add in slab.h to make sure things keep compiling.

Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20 11:11:14 -07:00
Dan Carpenter 7eaf8b9f0b clk: socfpga: remove a stray tab
This line was indented too far.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-06-09 18:14:27 -07:00
Dinh Nguyen 761d3e328c clk: socfpga: make use of of_clk_parent_fill helper function
Use of_clk_parent_fill to fill in the parent clock's array.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-05 18:10:34 -07:00
Dinh Nguyen 5343325ff3 clk: socfpga: add a clock driver for the Arria 10 platform
The clocks on the Arria 10 platform is a bit different than the
Cyclone/Arria 5 platform that it should just have it's own
driver.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-21 15:16:04 -07:00
Dinh Nguyen 5611a5ba8e clk: socfpga: update clk.h so for Arria10 platform to use
There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define
SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver
can use.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-21 15:10:38 -07:00
Stephen Boyd e45310bfcd clk: socfpga: Silence sparse warning
drivers/clk/socfpga/clk-periph.c:79:39: warning: Using plain integer as NULL pointer

Cc: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-14 17:11:28 -07:00
Stephen Boyd b011d386e9 clk: socfpga: Silence sparse warning
drivers/clk/socfpga/clk-gate.c:227:40: warning: Using plain integer as NULL pointer

Cc: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-14 17:11:25 -07:00
Mike Turquette a854aea24c Adds support getting the divider registers for the MAIN PLL that was once
thought to be hidden.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJTcQUFAAoJEBmUBAuBoyj0hFkP/2lSyq+o4swmhovXFV8xLlvg
 lgIq7m7RXqc8kSbz7RhbVOmjvTr7Kb5YRBQO7mIqJQpM/4lzUrsgGc9m7LZc6Rnh
 eP4Dt37gHCmacEwtjRp5nvQ5t0NaXXocctyb0LHKjuDRJlNkqd6Qcx+Lj4fXjsCf
 flWAxJN2ZG5BA8m5KCWPemYjiQblQUKNphphjte1AWgvl/yyzOSLneobnfdMFbiR
 jkaUBAw2vUYvz4NjJzw9f1aS8EUpc2IO6tLXERVZ7V6+rCakHK+DH1tzstlfqES0
 zIdEzoV1PzBiIreptLGH9EbM8nmFIX/7whijtEvOoxkHeLPtTUnTm0Mv0KGVR5wF
 k3tMPeNP0BDNJ/69nPnxbr7dSw1xkLU9UavY+/t7Jq5fAt4/DsOoPxRnbxOQI+SM
 Lf3KS+j7nLQ7ueOgaB7tiDS5unNRqaY0ys0MggeA9xA544gcTf/2sg/qS9ur7PP5
 jJ0yumtyunDCCI2xh0vUOipHNb0wbx9gCylgvPzatB8kDYaInOLA+ifVo9GJECd4
 jdKoS848wBYZESSaiEGGL5VcLhKAhE4ycLpsWHh5wFScr+4KfBVr/vcm2cZs3XIG
 ISANaRoDFOtk8jCwNw2wTveW1tLsQHFU1ldoMfFcvKzESQkoe4PM+s4waRLduPLx
 3OjACqD98ydI76tNli0f
 =anDE
 -----END PGP SIGNATURE-----

Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga

Adds support getting the divider registers for the MAIN PLL that was once
thought to be hidden.
2014-05-12 19:11:13 -07:00
Dinh Nguyen 0691bb1b5a clk: socfpga: add divider registers to the main pll outputs
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.

This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-05-12 12:27:22 -05:00
Dinh Nguyen a30d27ed73 clk: socfpga: fix clock driver for 3.15
commit [1771b10d6 clk: respect the clock dependencies in of_clk_init]
exposed a flaw in the socfpga clock driver and prevents the platform
from booting on 3.15-rc1.

Because the "altr,clk-mgr" is not really a clock, it should not be using
CLK_OF_DECLARE, instead we should be mapping the clk-mgr's base address
one of the functional clock init function. Use the socfpga_pll_init function
to map the clk_mgr_base_addr as this clock should always be initialized first.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Tested-by: Pavel Machek <pavel@denx.de>
2014-04-30 11:44:01 -07:00
Dinh Nguyen 95bb9f515f clk: socfpga: Fix section mismatch warning
WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in
reference from the variable socfpga_child_clocks to the function
.init.text:socfpga_pll_init()
The variable socfpga_child_clocks references
the function __init socfpga_pll_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in
reference from the variable socfpga_child_clocks to the function
.init.text:socfpga_periph_init()
The variable socfpga_child_clocks references
the function __init socfpga_periph_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in
reference from the variable socfpga_child_clocks to the function
.init.text:socfpga_gate_init()
The variable socfpga_child_clocks references
the function __init socfpga_gate_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

Reported-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-18 23:42:35 -07:00
Dinh Nguyen b89cd950cb clk: socfpga: Support multiple parents for the pll clocks
The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26 12:23:40 -08:00
Dinh Nguyen 5585f73175 clk: socfpga: Fix integer overflow in clock calculation
Use 64-bit integer for calculating clock rate. Also use do_div for the
64-bit division.

Signed-off-by: Graham Moore <grmoore@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26 12:23:29 -08:00
Dinh Nguyen 044abbde7b clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
---
v9: none
v8: Use degrees in the clk-phase binding property
v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
    prepare function to the gate clk that will toggle clock phase setting.
    Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
    set the phase shift settings.
v5: Use the "snps,dw-mshc" binding
v4: Use the sdmmc_clk prepare function to set the phase shift settings
v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
    loaded after the clock driver.
v2: Use the syscon driver
2014-02-18 14:08:14 -08:00
Steffen Trumtrar 97259e99bd clk: socfpga: split clk code
Move the different kinds of clocks into their own files. The reason is to aid
readability of the code. This also goes along with the other SoC-specific
clock drivers.

The split introduces new structs for the three types of clocks and uses them.
Other changes are not done to the code.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18 14:08:13 -08:00
Steffen Trumtrar 0c5a1872ba clk: socfpga: fix define typo
It should be SOCFPGA instead of SOCFGPA.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18 14:08:12 -08:00
Steffen Trumtrar ef5043c2d9 clk: socfpga: remove unused field
The clk_name field from the socfpga_clk struct is unused.
Remove it.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18 14:08:10 -08:00
Dinh Nguyen 77f1057777 clk: socfpga: Remove socfpga_init_clocks
The only thing that socfpga_init_clocks was doing is setting up the smp_twd clk.
Now that twd-timer's clock phandle is populated in the DTS, we can remove
this function.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-02-18 14:08:09 -08:00
Dinh Nguyen b7cec13f08 clk: socfpga: Look for the GPIO_DB_CLK by its offset
After the patch:
"clk: socfpga: Map the clk manager base address in the clock driver"

The clk->name field in socfpga_clk_recalc_rate() was getting cleared. Replace
looking for the GPIO_DB_CLK by its divider offset instead.

Also rename the define SOCFPGA_DB_CLK_OFFSET -> SOCFPGA_GPIO_DB_CLK_OFFSET, as
this represents the GPIO_DB_CLK.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18 14:08:08 -08:00
Dinh Nguyen 6a7e71221d clk: socfpga: Map the clk manager base address in the clock driver
The clk manager's base address was being mapped in SOCFPGA's arch code and
being extern'ed out to the clock driver. This method is not correct, and the
arch code was not really doing anything with that clk manager anyways.

This patch moves the mapping of the clk manager's base address in the clock
driver itself. Cleans up CLK_OF_DECLARE() into a single registration of all
the clocks.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
v2: Use a static declaration for the clk_mgr_base_addr. Clean up the
    CLK_OF_DECLARE() as suggested by Arnd.
2014-02-18 14:08:07 -08:00
Sachin Kamat 6d7ff6cc9c clk: socfpga: Use NULL instead of 0
'div_reg' is a pointer. Assign NULL instead of 0.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-19 17:47:32 -08:00
Dinh Nguyen 4d04391cfe clk: socfpga: Remove check for "reg" property in socfpga_clk_init
The function socfpga_clk_init() can support clocks that do not have a divider
register, but a fixed-divider that can be read from DTS. Therefore, the "reg"
property is not a failing condition for socfpga_clk_init().

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-11-27 12:48:51 -08:00
Dinh Nguyen 79a2e99889 clk: socfpga: Fix incorrect sdmmc clock name
The SD/MMC clock is named "sdmmc_clk", and NOT "mmc_clk". Because of this,
the SD driver was getting the incorrect clock value. This prevented the
SD driver from initializing correctly.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-10-07 18:37:49 -07:00
Dinh Nguyen 825f0c2672 ARM: socfpga: Add support to gate peripheral clocks
Add support to gate the clocks that directly feed peripherals. For clocks
with multiple parents, add the ability to determine the correct parent,
and also set parents. Also add support to calculate and set the clocks'
rate.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Cc: Mike Turquette <mturquette@linaro.org>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
CC: <linux@arm.linux.org.uk>

v4:
- Add Acked-by: Mike Turquette

v3:
- Addressed comments from Pavel

v2:
- Fix space/indent errors
- Add streq for strcmp == 0
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-11 16:35:29 -07:00
Dinh Nguyen 56c5c13f70 ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries
With this patch, the socfpga clk driver is able to query the clock and clock
rates appropriately.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-14 20:18:13 -07:00
Dinh Nguyen 66314223aa ARM: socfpga: initial support for Altera's SOCFPGA platform
Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-07-19 10:39:00 +02:00