Commit Graph

3 Commits

Author SHA1 Message Date
Chris Zankel b67360db14 [XTENSA] Flush the page-address in update-mmu instead of user-address
The TLB entry for the user address doesn't exist at the time we
want to flush the caches, so use the page address. Note that processor
configurations with cache-aliasing issues are treated separately.

Signed-off-by: Chris Zankel <chris@zankel.net>
2008-02-13 16:58:51 -08:00
Chris Zankel 1e12e3919e [XTENSA] Remove duplicate includes.
Signed-off-by: Lucas Woods <woodzy@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Christian Zankel <chris@zankel.net>
2008-02-13 15:05:35 -08:00
Chris Zankel 6656920b0b [XTENSA] Add support for cache-aliasing
Add support for processors that have cache-aliasing issues, such as
the Stretch S5000 processor. Cache-aliasing means that the size of
the cache (for one way) is larger than the page size, thus, a page
can end up in several places in cache depending on the virtual to
physical translation. The method used here is to map a user page
temporarily through the auto-refill way 0 and of of the DTLB.
We probably will want to revisit this issue and use a better
approach with kmap/kunmap.

Signed-off-by: Chris Zankel <chris@zankel.net>
2007-08-27 13:54:16 -07:00