Commit Graph

5 Commits

Author SHA1 Message Date
Simran Rai bcd8be1398 clk: iproc: Add support for Cygnus audio clocks
This patch adds support for Broadcom Cygnus audio PLL and leaf
clocks

Signed-off-by: Simran Rai <ssimran@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:31:38 -08:00
Jon Mason 40c8bec3f2 clk: iproc: Separate status and control variables
Some PLLs have separate registers for Status and Control.  The means the
pll_base needs to be split into 2 new variables, so that those PLLs can
specify device tree registers for those independently.  Also, add a new
driver flag to identify this presence of the split, and let the driver
know that additional registers need to be used.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21 17:03:41 -07:00
Jon Mason f713c6bf32 clk: iproc: Split off dig_filter
The PLL loop filter/gain can be located in a separate register on some
SoCs.  Split these off into a separate variable, so that an offset can
be added if necessary.  Also, make the necessary modifications to the
Cygnus and NSP drivers for this change.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21 17:02:57 -07:00
Jon Mason 01b6722fdf clk: iproc: Add PWRCTRL support
Some iProc SoC clocks use a different way to control clock power, via
the PWRDWN bit in the PLL control register.  Since the PLL control
register is used to access the PWRDWN bit, there is no need for the
pwr_base when this is being used.  A new flag, IPROC_CLK_EMBED_PWRCTRL,
has been added to identify this usage.  We can use the AON interface to
write the values to enable/disable PWRDOWN.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
[sboyd@codeaurora.org: Remove useless parentheses]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21 16:53:15 -07:00
Ray Jui 5fe225c105 clk: iproc: add initial common clock support
This adds basic and generic support for various iProc PLLs and clocks
including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks.

SoCs under the iProc architecture can define their specific register
offsets and clock parameters for their PLL and clock controllers. These
parameters can be passed as arugments into the generic iProc PLL and
clock setup functions

Derived from code originally provided by Jonathan Richardson
<jonathar@broadcom.com>

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-06-18 12:36:38 -07:00