Commit Graph

195 Commits

Author SHA1 Message Date
Jerome Brunet 7df533a7e3 clk: meson: add gen_clk
GEN_CLK is able to route several internal clocks to one of the SoC
pads. In the future, even more clocks could be made accessible using
cts_msr_clk - the clock measure block.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:49:31 +02:00
Jerome Brunet 80d396b511 clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition

Fixes: 738f66d321 ("clk: gxbb: add AmLogic GXBB clk controller driver")
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:49:22 +02:00
Yixun Lan cddcb20b2b clk: meson-axg: add clocks required by pcie driver
Adding clocks for the pcie driver. Due to the ASIC design,
the pcie controller re-use part of the mipi clock logic,
so the mipi clock is also added.

Tested-by: Jianxin Qin <jianxin.qin@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[amended to remove unnecessary locales]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:49:11 +02:00
Jerome Brunet 85ddc1a32c clk: meson: remove unused clk-audio-divider driver
clk-audio-divider is no longer used, we can remove it.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:48:59 +02:00
Jerome Brunet 9799d5ae00 clk: meson: stop rate propagation for audio clocks
It is actually a lot easier to setup the PLL with carefully chosen rates
than relying on CCF clock propagation for this audio use case.
This way, we can make sure we will always be able to provide the common
audio clock rates, while having the PLL in the optimal operating range.

For this, we stop the rate propagation at the mux picking the
PLL and let it round to the closest matching PLL.

Doing so, we can use the generic divider for the i2s clock.
clk-audio-divider is no longer required. It was a (poor) attempt
to use CCF rate propagation while making sure the PLL rate would
be high enough to work with audio use cases.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:48:59 +02:00
Jerome Brunet 1cd5018175 clk: meson: axg: add the audio clock controller driver
The axg audio clock controller is the clock generation unit for the
amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
different plls provided by the primary clock controller and also by
10 slave bit clocks and 10 slave sample clocks which may be provided
by external components, such as audio codecs, through the SoC pads.

It contains several muxes, dividers and gates which are fed into the
the different devices of the audio subsystem.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:48:26 +02:00
Jerome Brunet 3054a55c5d clk: meson: add axg audio sclk divider driver
Add a driver to control the clock divider found in the sample clock
generator of the axg audio clock controller.

The sclk divider accumulates specific features which make the generic
divider unsuitable to control it:
- zero based divider (div = val + 1), but zero value gates the clock,
  so minimum divider value is 2.
- lrclk variant may adjust the duty cycle depending the divider value
  and the 'hi' value.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:48:25 +02:00
Jerome Brunet e8dd920776 clk: meson: add triple phase clock driver
Add a driver to control the output of the sample clock generator found
in the axg audio clock controller.

The goal of this driver is to coherently control the phase provided to
the different element using the sample clock generator. This simplify
the usage of the sample clock generator a lot, without comprising the
ability of the SoC.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:47:22 +02:00
Jerome Brunet 47f21315a6 clk: meson: add clk-phase clock driver
Add a driver based meson clk-regmap to control clock phase on
amlogic SoCs

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:47:22 +02:00
Jerome Brunet 443f228578 clk: meson: clean-up meson clock configuration
Clean the dependencies in meson clock Kconfig.
CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also,
each platform should select CLK_AMLOGIC, so everything is properly turned
on when the platform Kconfig enable each configuration flag

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:46:21 +02:00
Jerome Brunet 60e267f3fd clk: meson: remove obsolete register access
The legacy method to access the hhi register space is not longer used.
We can safely drop it now.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:46:21 +02:00
Jerome Brunet 7813c14c94 clk: meson: audio-divider is one based
The audio divider is one based. This offset was mistakenly dropped from
recalc_rate() when migrating to clk_regmap.

Fixes: 88a4e12836 ("clk: meson: migrate the audio divider clock to clk_regmap")
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-06-21 10:10:50 +02:00
Neil Armstrong c987ac6f1f clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL
On Amlogic Meson GXBB & GXL platforms, the SCPI Cortex-M4 Co-Processor
seems to be dependent on the FCLK_DIV2 to be operationnal.

The issue occurred since v4.17-rc1 by freezing the kernel boot when
the 'schedutil' cpufreq governor was selected as default :

  [   12.071837] scpi_protocol scpi: SCP Protocol 0.0 Firmware 0.0.0 version
  domain-0 init dvfs: 4
  [   12.087757] hctosys: unable to open rtc device (rtc0)
  [   12.087907] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  [   12.102241] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

But when disabling the MMC driver, the boot finished but cpufreq failed to
change the CPU frequency :

  [   12.153045] cpufreq: __target_index: Failed to change cpu frequency: -5

A bisect between v4.16 and v4.16-rc1 gave
05f814402d ("clk: meson: add fdiv clock gates") to be the first bad commit.
This commit added support for the missing clock gates before the fixed PLL
fixed dividers (FCLK_DIVx) and the clock framework basically disabled
all the unused fixed dividers, thus disabled a critical clock path for
the SCPI Co-Processor.

This patch simply sets the FCLK_DIV2 gate as critical to ensure
nobody can disable it.

Fixes: 05f814402d ("clk: meson: add fdiv clock gates")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[few corrections in the commit description]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-06-19 17:20:11 +02:00
Linus Torvalds 6419945e33 This time we have a good set of changes to the core framework that do some
general cleanups, but nothing too major. The majority of the diff goes to
 two SoCs, Actions Semi and Qualcomm. A brand new driver is introduced for
 Actions Semi so it takes up some lines to add all the different types, and
 the Qualcomm diff is there because we add support for two SoCs and it's quite
 a bit of data.
 
 Otherwise the big driver updates are on TI Davinci and Amlogic platforms. And
 then the long tail of driver updates for various fixes and stuff follows
 after that.
 
 Core:
  - debugfs cleanups removing error checking and an unused provider API
  - Removal of a clk init typedef that isn't used
  - Usage of match_string() to simplify parent string name matching
  - OF clk helpers moved to their own file (linux/of_clk.h)
  - Make clk warnings more readable across kernel versions
 
 New Drivers:
  - Qualcomm SDM845 GCC and Video clk controllers
  - Qualcomm MSM8998 GCC
  - Actions Semi S900 SoC support
  - Nuvoton npcm750 microcontroller clks
  - Amlogic axg AO clock controller
 
 Removed Drivers:
  - Deprecated Rockchip clk-gate driver
 
 Updates:
  - debugfs functions stopped checking return values
  - Support for the MSIOF module clocks on Rensas R-Car M3-N
  - Support for the new Rensas RZ/G1C and R-Car E3 SoCs
  - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs
  - Berlin and Amlogic SPDX tagging
  - Usage of of_clk_get_parent_count() in more places
  - Proper implementation of the CDEV1/2 clocks on Tegra20
  - Allwinner H6 PRCM clock support and R40 EMAC support
  - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet
  - Round closest support for meson's mpll driver
  - Support for meson8b nand clocks and gxbb video decoder clocks
  - Mediatek mali clks
  - STM32MP1 fixes
  - Uniphier LD11/LD20 stream demux system clock
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This time we have a good set of changes to the core framework that do
  some general cleanups, but nothing too major. The majority of the diff
  goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is
  introduced for Actions Semi so it takes up some lines to add all the
  different types, and the Qualcomm diff is there because we add support
  for two SoCs and it's quite a bit of data.

  Otherwise the big driver updates are on TI Davinci and Amlogic
  platforms. And then the long tail of driver updates for various fixes
  and stuff follows after that.

  Core:
   - debugfs cleanups removing error checking and an unused provider API
   - Removal of a clk init typedef that isn't used
   - Usage of match_string() to simplify parent string name matching
   - OF clk helpers moved to their own file (linux/of_clk.h)
   - Make clk warnings more readable across kernel versions

  New Drivers:
   - Qualcomm SDM845 GCC and Video clk controllers
   - Qualcomm MSM8998 GCC
   - Actions Semi S900 SoC support
   - Nuvoton npcm750 microcontroller clks
   - Amlogic axg AO clock controller

  Removed Drivers:
   - Deprecated Rockchip clk-gate driver

  Updates:
   - debugfs functions stopped checking return values
   - Support for the MSIOF module clocks on Rensas R-Car M3-N
   - Support for the new Rensas RZ/G1C and R-Car E3 SoCs
   - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs
   - Berlin and Amlogic SPDX tagging
   - Usage of of_clk_get_parent_count() in more places
   - Proper implementation of the CDEV1/2 clocks on Tegra20
   - Allwinner H6 PRCM clock support and R40 EMAC support
   - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet
   - Round closest support for meson's mpll driver
   - Support for meson8b nand clocks and gxbb video decoder clocks
   - Mediatek mali clks
   - STM32MP1 fixes
   - Uniphier LD11/LD20 stream demux system clock"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits)
  clk: qcom: Export clk_fabia_pll_configure()
  clk: bcm: Update and add Stingray clock entries
  dt-bindings: clk: Update Stingray binding doc
  clk-si544: Properly round requested frequency to nearest match
  clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
  clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
  clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
  clk: ingenic: jz4770: Change OTG from custom to standard gated clock
  clk: ingenic: Support specifying "wait for clock stable" delay
  clk: ingenic: Add support for clocks whose gate bit is inverted
  clk: use match_string() helper
  clk: bcm2835: use match_string() helper
  clk: Return void from debug_init op
  clk: remove clk_debugfs_add_file()
  clk: tegra: no need to check return value of debugfs_create functions
  clk: davinci: no need to check return value of debugfs_create functions
  clk: bcm2835: no need to check return value of debugfs_create functions
  clk: no need to check return value of debugfs_create functions
  clk: imx6: add EPIT clock support
  clk: mvebu: use correct bit for 98DX3236 NAND
  ...
2018-06-09 12:06:24 -07:00
Jerome Brunet de1ca2d07b clk: meson: axg: let mpll clocks round closest
Let the mpll dividers achieve the closest rate possible, even if
it means rounding the requested rate up.

This is done to improve the accuracy of the rates provided by these
plls to the audio subsystem

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-21 11:31:59 +02:00
Jerome Brunet bae1106c37 clk: meson: mpll: add round closest support
Allow the mpll driver to round the requested rate up if
CLK_MESON_MPLL_ROUND_CLOSEST is set and it provides a rate closer to the
requested rate.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-21 11:31:29 +02:00
Martin Blumenstingl 72e1f23020 clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
Until commit 05f814402d ("clk: meson: add fdiv clock gates") we
relied on the bootloader to enable the fclk_div clock gates. It turns
out that our clock tree is incomplete at least on Meson8b (tested with
an Odroid-C1, which uses an RGMII PHY) because after the mentioned
commit Ethernet is not working anymore (no RX/TX activity can be seen).
At the same time Ethernet was still working on Meson8m2 with a RMII PHY.

Testing has shown that as soon as "fclk_div2" is disabled Ethernet stops
working on Odroid-C1. Unfortunately it's currently not clear what the
Ethernet controller IP block uses the fclk_div2 clock for. Mark the
clock as CLK_IS_CRITICAL to keep it enabled (as it's already enabled by
most bootloaders by default, which is why we didn't notice it before).

Fixes: 05f814402d ("clk: meson: add fdiv clock gates")
Cc: stable@vger.kernel.org
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-21 10:33:58 +02:00
Jerome Brunet 22f65a389f clk: meson: use SPDX license identifiers consistently
Replace every license notices in drivers/clk/meson by SPDX license
identifiers, as described in license-rules.rst

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-18 12:08:29 +02:00
Yixun Lan 24a2e6796e clk: meson: drop CLK_SET_RATE_PARENT flag
The clk81 is not expected to be changed, so drop this flag.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-15 14:19:43 +02:00
Qiufang Dai 6693e2199e clk: meson-axg: Add AO Clock and Reset controller driver
Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.

Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-15 14:19:43 +02:00
Yixun Lan 88e2da8124 clk: meson: aoclk: refactor common code into dedicated file
We try to refactor the common code into one dedicated file,
while preparing to add new Meson-AXG aoclk driver, this would
help us to better share the code by all aoclk drivers.

Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-15 14:19:42 +02:00
Yixun Lan bdfa6394c2 clk: meson: migrate to devm_of_clk_add_hw_provider API
There is a protential memory leak, as of_clk_del_provider is
never called if of_clk_add_hw_provider has been executed.
Fix this by using devm variant API.

Fixes: f8c11f7991 ("clk: meson: Add GXBB AO Clock and Reset controller driver")
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-15 14:18:38 +02:00
Maxime Jourdan a565242eb9 clk: meson: gxbb: add the video decoder clocks
Add the SEL/DIV/GATE for VDEC_1 and VDEC_HEVC.

Signed-off-by: Maxime Jourdan <maxi.jourdan@wanadoo.fr>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-15 14:18:38 +02:00
Martin Blumenstingl b8c1ddadc8 clk: meson: meson8b: add support for the NAND clocks
This adds the NAND clocks (from the HHI_NAND_CLK_CNTL register) to the
Meson8b clock driver. There are three NAND clocks: a gate which enables
or disables the NAND clock, a mux and a divider (which divides the mux
output).
Unfortunately the public S805 datasheet does not document the mux
parents. However, the vendor kernel has a few hints for us which allows
us to make an educated guess about the clock parents. To do this we need
to have a look at set_nand_core_clk() from the vendor's NAND driver (see
[0]):
- XTAL = (4<<9) | (1<<8) | 0
- 160MHz = (0<<9) | (1<<8) | 3)
- 182MHz = (3<<9) | (1<<8) | 1)
- 212MHz = (1<<9) | (1<<8) | 3)
- 255MHz = (2<<9) | (1<<8) | 1)

While there is a comment for the XTAL parent (which indicates that it
should only be used for debugging) we have to do a bit of math for the
other parents: target_freq * divider = rate of parent clock
Bit 8 above is the enable bit, so we can ignore it here. Bits 11:9 are
the mux index and bits 6:0 are the 0-based divider (so we need to add
1). This gives us:
- mux 0 (160MHz * 4) = fclk_div4 (actual rate = 637.5MHz, off by 2.5MHz)
- mux 1 (212MHz * 4) = fclk_div3 (actual rate = 850MHz, off by 2MHz)
- mux 2 (255MHz * 2) = fclk_div5 (matches exactly 510MHz)
- mux 3 (182MHz * 2) = fclk_div7 (actual rate = 346.3MHz, off by 0.3MHz)

[0] https://github.com/khadas/linux/blob/9587681285cb/drivers/amlogic/amlnf/dev/amlnf_ctrl.c#L314

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-15 14:18:38 +02:00
Stephen Boyd c964cfc612 First round of fixes for meson clocks targeted for v4.17
- fix typos in two meson8 clock names
  - remove unused clock ops declaration
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Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson into clk-fixes

Pull meson clk fixes from Jerome Brunet:
 - fix typos in two meson8 clock names
 - remove unused clock ops declaration

* tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: fix meson8b_cpu_clk parent clock name
  clk: meson: meson8b: fix meson8b_fclk_div3_div clock name
  clk: meson: drop meson_aoclk_gate_regmap_ops
2018-05-01 14:44:16 -07:00
Martin Blumenstingl 5b33139b1a clk: meson: meson8b: fix meson8b_cpu_clk parent clock name
meson8b_cpu_clk has two parent clocks:
- meson8b_xtal
- meson8b_cpu_scale_out_sel

The name of the "xtal" clock parent is specified correctly. However,
there is a typo in the name of the second parent clock. The
meson8b_cpu_scale_out_sel definition uses the name "cpu_scale_out_sel"
(which matches the name from the datasheet). However, the mux parent
definition uses the name "cpu_out_sel" which does not match any existing
clock.

Fixes: 251b6fd38b ("clk: meson: rework meson8b cpu clock")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-04-25 10:23:19 +02:00
Martin Blumenstingl b251e4c88f clk: meson: meson8b: fix meson8b_fclk_div3_div clock name
The names of all fclk divider gate clocks follow the naming schema
"fclk_divN" and the name of all fclk fixed dividers follow the naming
schema "fclk_divN_div".
There's one exception to this rule: meson8b_fclk_div3_div's name is
"fclk_div_div3". It's child clock meson8b_fclk_div3 however references
it as "fclk_div3_div" (following the naming schema explained above).

Fix the naming of the meson8b_fclk_div3_div clock to follow the naming
schema. This also fixes serial console on my Meson8m2 board because
"clk81" uses fclk_div3 as parent. However, since the hierarchy stops at
meson8b_fclk_div3 there's no known parent clock and the rate of "clk81"
and all of it's children (UART clock, SDIO MMC controller clock, ...)
are all 0.

Fixes: 05f814402d ("clk: meson: add fdiv clock gates")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-04-25 10:21:35 +02:00
Yixun Lan 197143feed clk: meson: drop meson_aoclk_gate_regmap_ops
let's remove the unused meson_aoclk_gate_regmap_ops

Fixes: 1f932d9971 ("clk: meson: remove superseded aoclk_gate_regmap")
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-04-25 10:19:26 +02:00
Jerome Brunet 6cc1eb5078 clk: meson: honor CLK_MUX_ROUND_CLOSEST in clk_regmap
Using __clk_mux_determine_rate effectively ignores CLK_MUX_ROUND_CLOSEST
if set the related clk_regmap mux instance.

Use clk_mux_determine_rate_flags() to make sure the flag is honored.

Fixes: ea11dda9e0 ("clk: meson: add regmap clocks")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-16 09:25:09 -07:00
Stephen Boyd 5d1c04dde0 clk: meson: Drop unused local variable and add static
Fixes the following warnings:

drivers/clk/meson/meson8b.c:512:19: warning: symbol 'meson8b_mpeg_clk_div' was not declared. Should it be static?
drivers/clk/meson/meson8b.c:526:19: warning: symbol 'meson8b_clk81' was not declared. Should it be static?
drivers/clk/meson/meson8b.c:540:19: warning: symbol 'meson8b_cpu_in_sel' was not declared. Should it be static?
drivers/clk/meson/meson8b.c:591:19: warning: symbol 'meson8b_cpu_scale_div' was not declared. Should it be static?
drivers/clk/meson/meson8b.c:608:19: warning: symbol 'meson8b_cpu_scale_out_sel' was not declared. Should it be static?
drivers/clk/meson/meson8b.c:626:19: warning: symbol 'meson8b_cpu_clk' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:392:27: warning: symbol 'gxbb_gp0_init_regs' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:439:27: warning: symbol 'gxl_gp0_init_regs' was not declared. Should it be static?
drivers/clk/meson/axg.c:195:27: warning: symbol 'axg_gp0_init_regs' was not declared. Should it be static?
drivers/clk/meson/axg.c:248:27: warning: symbol 'axg_hifi_init_regs' was not declared. Should it be static?
drivers/clk/meson/meson8b.c: In function 'meson8b_clkc_probe':
drivers/clk/meson/meson8b.c:1052:14: warning: unused variable 'clk' [-Wunused-variable]

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-14 15:36:31 -07:00
Jerome Brunet 5b13ef64ee clk: meson: clean-up clk81 clocks
clk81 is a composite clock which parents all the peripheral clocks of the
platform. It is a critical clock which is used as provided by the
bootloader. We don't want to change its rate or reparent it, ever.

Remove the CLK_IGNORE_UNUSED on the mux and divider. These clock can't
gate so the flag is useless, and the gate is already critical, so the
clock won't ever be unused.

Remove CLK_SET_RATE_NO_REPARENT from mux, it is useless since the mux is
read-only.

Remove CLK_SET_RATE_PARENT from the gate and divider and use ro_ops for
the divider. A peripheral clock should not try to change the rate of
clk81. Stopping the rate propagation is good way to make sure such request
would be ignored.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:10:00 +01:00
Jerome Brunet 05f814402d clk: meson: add fdiv clock gates
Fdiv fixed dividers clocks of the fixed_pll can actually gate
independently. We never had an issue so far because these clocks
were provided 'enabled' by the bootloader.

Add these gates to enable/disable the clocks when required.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:58 +01:00
Jerome Brunet 513b67ac39 clk: meson: add mpll pre-divider
mpll clocks parent can actually be divided by 1 or 2. So far, this
divider has always been set to 1, so the calculation was correct.
Now that we know it exists, model the tree correctly. If we ever get
a platform where the divider is different, we won't get into trouble

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:56 +01:00
Jerome Brunet 093c3fac46 clk: meson: axg: add hifi pll clock
Add the hifi pll to the axg clock controller. This clock maybe used as an
input of the axg audio clock controller. It uses the same settings table
as the gp0 pll but has a frac parameter allowing more precision.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:54 +01:00
Jerome Brunet 0a1be867b9 clk: meson: add ROUND_CLOSEST to the pll driver
Provide an option for the pll driver to round to the rate closest to the
requested rate, instead of systematically rounding down.

This may allow the provided rate to be closer to the requested rate when
rounding up is not an issue

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:49 +01:00
Jerome Brunet c77de0e5c9 clk: meson: add gp0 frac parameter for axg and gxl
Add the frac parameter for the gp0 pll of the axg and gxl.
This allows to achieve rates between the fixed settings provided
by the table.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:47 +01:00
Jerome Brunet 8289aafa4f clk: meson: improve pll driver results with frac
Finding the appropriate settings of meson plls is too tricky to be done
entirely at runtime, using calculation only. Many combination of m, n
and od won't lock which is why we are using a table for this.  However,
for plls having a fractional parameters, it is possible to improve on
the result provided by the table by calculating the frac parameter.

This change adds the calculation of frac when the parameter is available
and the rate provided by the table is not an exact match for the
requested rate.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:45 +01:00
Jerome Brunet c178b003bf clk: meson: remove special gp0 lock loop
After testing, it appears that the gxl (and axg) does not require the
special locking/reset loop which was initially added for it.

All the values present in the gxl table can locked with the simple lock
checking loop.

The change switches the gxl and axg gp0 back to the simple lock checking
loop and removes the code no longer required.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:38 +01:00
Jerome Brunet 117863e842 clk: meson: poke pll CNTL last
Poking CNTL first may take the PLL out of reset while we are still
applying the initial settings, including the filter values
initialization. This is the case for the axg and gxl gp0 pll.

Doing this poke last ensures the pll stays in reset while the initial
settings are applied.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:36 +01:00
Jerome Brunet 2eab2d7cab clk: meson: add fractional part of meson8b fixed_pll
Add the missing frac parameter to the meson8b fixed_pll. It seems to be
always on this platform, so the rate remains unchanged

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:33 +01:00
Jerome Brunet 4162dd5b3a clk: meson: use hhi syscon if available
On gxbb and axg, try to get the hhi regmap from the parent DT node, which
should be the HHI system controller once the necessary changes have been
made in amlogic's DTs

Until then, if getting regmap through the system controller fails, the
clock controller will fall back to the old way, requesting memory region
directly and then registering the regmap itself.

This should allow a smooth transition to syscon

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:04 +01:00
Jerome Brunet 03a6519e9c clk: meson: remove obsolete cpu_clk
meson8b cpu_clk has been replaced by a set of divider and mux clocks.
meson_cpu_clk is no longer used and can be removed

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:04 +01:00
Jerome Brunet 251b6fd38b clk: meson: rework meson8b cpu clock
Instead of migrating meson cpu_clk to clk_regmap, like the other meson
clock drivers, we take advantage of the massive rework to get rid of it
completely, and solve (the first part) of the related FIXME notice.

As pointed out in the code comments, the cpu_clk should be modeled with
dividers and muxes it is made of, instead of one big composite clock.

The cpu_clk was not working correctly to enable dvfs on meson8b. It hangs
quite often when changing the cpu clock rate. This new implementation,
based on simple elements improves the situation but the platform will
still hang from time to time. This is not acceptable so, until we can
make the mechanism around the cpu clock stable, the cpu clock subtree
has been put in read-only mode, preventing any change of the cpu clock

The notifier and read-write operation will be added back when we have a
solution to the problem.

Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:03 +01:00
Jerome Brunet d610b54f77 clk: meson: split divider and gate part of mpll
The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.

This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:03 +01:00
Jerome Brunet 722825dcd5 clk: meson: migrate plls clocks to clk_regmap
Rework meson pll driver to use clk_regmap and move meson8b, gxbb and
axg's clock using meson_clk_pll to clk_regmap.

This rework is not just about clk_regmap, there a serious clean-up of
the driver code:
* Add lock and reset field: Previously inferred from the n field.
* Simplify the reset logic: Code seemed to apply reset differently but
  in fact it was always the same -> assert reset, apply params,
  de-assert reset. The 2 lock checking loops have been kept for now, as
  they seem to be necessary.
* Do the sequence of init register pokes only at .init() instead of in
  .set_rate(). Redoing the init on every set_rate() is not necessary

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:03 +01:00
Jerome Brunet 88a4e12836 clk: meson: migrate the audio divider clock to clk_regmap
Rework meson audio divider driver to use clk_regmap and move gxbb
clock using meson_clk_audio_divider to clk_regmap.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:02 +01:00
Jerome Brunet c763e61ae8 clk: meson: migrate mplls clocks to clk_regmap
Rework meson mpll driver to use clk_regmap and move meson8b, gxbb
and axg clocks using meson_clk_mpll to clk_regmap

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:02 +01:00
Jerome Brunet f510c32a6a clk: meson: add regmap helpers for parm
Meson clock drivers are using struct parm to describe each field of the
clock provider. Providing helpers to access these fields with regmap
helps to keep drivers readable

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:01 +01:00
Jerome Brunet 2513a28c10 clk: meson: migrate muxes to clk_regmap
Move meson8b, gxbb and axg clocks using clk_mux to clk_regmap
Also remove a few useless tables in the process

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:01 +01:00
Jerome Brunet f06ddd2852 clk: meson: migrate dividers to clk_regmap
Move meson8b, gxbb and axg clocks using clk_divider to clk_regmap

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:00 +01:00