Commit Graph

26 Commits

Author SHA1 Message Date
Yuantian Tang 36ab046715 clk: qoriq: add more divider clocks support
More divider clocks are needed by IP. So enlarge the PLL divider
array to accommodate more divider clocks.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21 15:57:28 -08:00
Rob Herring 1667393126 clk: Convert to using %pOF instead of full_name
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-21 15:49:54 -07:00
Yuantian Tang 45899dc5f1 clk: qoriq: add pll clock to clock lookup table
Register each PLL and its division clocks to clock
lookup table to facilitate the clock look up for
clock consumer.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-21 15:01:45 -07:00
Yuantian Tang e0c888c4a2 clk: qoriq: add clock configuration for ls1088a soc
Clock on ls1088a chip takes primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP modules.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-21 15:01:44 -07:00
Scott Wood 80b4ae7ace clk: qoriq: Separate root input clock for core PLLs on ls1012a
ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.

Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-01 01:24:13 -07:00
Tang Yuantian 447093584f clk: qoriq: added ls1012a clock configuration
Acked-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[sboyd@codeaurora.org: Sorted list]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08 16:29:30 -08:00
Stephen Boyd a4315592e8 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: mmp: pxa910: fix return value check in pxa910_clk_init()
  clk: mmp: pxa168: fix return value check in pxa168_clk_init()
  clk: mmp: mmp2: fix return value check in mmp2_clk_init()
  clk: qoriq: Don't allow CPU clocks higher than starting value
2016-11-01 18:39:07 -07:00
Mingkai Hu 80e521987b clk: qoriq: add ls1046a support
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01 17:45:14 -07:00
Scott Wood 7c1c5413a7 clk: qoriq: Don't allow CPU clocks higher than starting value
The boot-time frequency of a CPU is considered its rated maximum, as we
have no other source of such information.  However, this was previously
only used for chips with 80% restrictions on secondary PLLs.  This
usually wasn't a problem because most chips/configs boot with a divider
of /1, with other dividers being used only for dynamic frequency
reduction.  However, at least one config (LS1021A at less than 1 GHz)
uses a different divider for top speed.  This was causing cpufreq to set
a frequency beyond the chip's rated speed.

This is fixed by applying a 100%-of-initial-speed limit to all CPU PLLs,
similar to the existing 80% limit that only applied to some.

Signed-off-by: Scott Wood <oss@buserror.net>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01 17:26:15 -07:00
Tang Yuantian 8964193f6b clk: qoriq: fix a register offset error
The offset of Core Cluster clock control/status register
on cluster group V3 version is different from others, and
should be plus 0x70000.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: Scott Wood <oss@buserror.net>
Fixes: 9e19ca2f62 ("clk: qoriq: Add ls2080a support.")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-18 16:52:24 -07:00
Julia Lawall 3432a2e397 clk: qoriq: add __init attribute
Add __init attribute on a function that is only called from other __init
functions and that is not inlined, at least with gcc version 4.8.4 on an
x86 machine with allyesconfig.  Currently, the function is put in the
.text.unlikely segment.  Declaring it as __init will cause it to be put in
the .init.text and to disappear after initialization.

The result of objdump -x on the function before the change is as follows:

0000000000000000 l     F .text.unlikely 0000000000000071 sysclk_from_fixed.constprop.5

And after the change it is as follows:

0000000000000480 l     F .init.text	000000000000006c sysclk_from_fixed.constprop.5

Done with the help of Coccinelle.  The semantic patch checks for local
static non-init functions that are called from an __init function and are
not called from any other function.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-19 18:56:15 -07:00
Stephen Boyd ec3f2fcb32 clk: qoriq: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Hou Zhiqiang <B48286@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 16:50:16 -07:00
Sudip Mukherjee 279104e3ad clk: qoriq: fix memory leak
If get_pll_div() fails we exited by returning NULL but we missed
releasing hwc.

Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Fixes: 0dfc86b317 ("clk: qoriq: Move chip-specific knowledge into driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-30 13:00:54 -08:00
Hou Zhiqiang e994412c5f clk: qoriq: Add ls1043a support.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-10-27 00:21:38 -05:00
Scott Wood 2c7693e081 clk: qoriq: Fix wrong data in p2041_cmux_grp2
Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-10-22 23:21:46 -05:00
Scott Wood 9e19ca2f62 clk: qoriq: Add ls2080a support.
LS2080A is the first implementation of the chassis 3 clockgen, which
has a different register layout than previous chips.  It is also little
endian, unlike previous chips.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21 18:05:55 -05:00
Scott Wood 0dfc86b317 clk: qoriq: Move chip-specific knowledge into driver
The device tree should describe the chips (or chip-like subblocks) in
the system, but it generally does not describe individual registers --
it should identify, rather than describe, a programming interface.

This has not been the case with the QorIQ clockgen nodes.  The
knowledge of what each bit setting of CLKCnCSR means is encoded in
three places (binding, pll node, and mux node), and the last also needs
to know which options are valid on a particular chip.  All three of
these locations are considered stable ABI, making it difficult to fix
mistakes (of which I have found several), much less refactor the
abstraction to be able to address problems, limitations, or new chips.

Under the current binding, a pll clock specifier of 2 means that the
PLL is divided by 4 -- and the driver implements this, unless there
happen to be four clock-output-names rather than 3, in which case it
interprets it as PLL divided by 3.  This does not appear in the binding
documentation at all.  That hack is now considered stable ABI.

The current device tree nodes contain errors, such as saying that
T1040 can set a core clock to PLL/4 when only PLL and PLL/2 are options.
The current binding also ignores some restrictions on clock selection,
such as p5020's requirement that if a core uses the "wrong" PLL, that
PLL must be clocked lower than the "correct" PLL and be at most 80% of
the rated CPU frequency.

Possibly because of the lack of the ability to express such nuance in
the binding, some valid options are omitted from the device trees, such
as the ability on p4080 to run cores 0-3 from PLL3 and cores 4-7 from
PLL1 (again, only if they are at most 80% of rated CPU frequency).
This omission, combined with excessive caution in the cpufreq driver
(addressed in a subsequent patch), means that currently on a 1500 MHz
p4080 with typical PLL configuration, cpufreq can lower the frequency
to 1200 MHz on half the CPUs and do nothing on the others.  With this
patchset, all CPUs can be lowered to 1200 MHz on a rev2 p4080, and on a
rev3 p4080 half can be lowered to 750 MHz and the other half to 600
MHz.

The current binding only deals with CPU clocks.  To describe FMan in
the device tree, we need to describe its clock.  Some chips have
additional muxes that work like the CPU muxes, but are not described in
the device tree.  Others require inspecting the Reset Control Word to
determine which PLL is used.  Rather than continue to extend this mess,
replace it.  Have the driver bind to the chip-specific clockgen
compatible, and keep the detailed description of quirky chip variations
in the driver, where it can be easily fixed, refactored, and extended.

Older device trees will continue to work (including a workaround for
old ls1021a device trees that are missing compatible and reg in the
clockgen node, which even the old binding required).  The pll/mux
details in old device trees will be ignored, but "clocks" properties
pointing at the old nodes will still work, and be directed at the
corresponding new clock.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21 18:05:52 -05:00
Emil Medve a513b72cc3 clk: qoriq: Add support for the platform PLL
Change-Id: Iac11ed95f274485a86d2c11f32a3dc502bcd020f
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Acked-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-18 09:56:43 -08:00
Emil Medve c88b2b662a clk: qoriq: Use pr_fmt()
Currently a mix of clk-qoriq/qoriq-clk and no prefix is used

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:40 -08:00
Emil Medve 6ef1ccac50 clk: qoriq: Replace kzalloc() with kmalloc()
Where the memset() is not necessary

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:40 -08:00
Emil Medve 334680dd51 clk: qoriq: Make local symbol 'static'
drivers/clk/clk-qoriq.c:59:22: warning: symbol 'cmux_ops' was not declared. Should it be static?

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:39 -08:00
Emil Medve 8002cab6ba clk: qoriq: Fix checkpatch type OOM_MESSAGE
WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!parent_names) {
+               pr_err("%s: could not allocate parent_names\n", __func__);

WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!cmux_clk) {
+               pr_err("%s: could not allocate cmux_clk\n", __func__);

WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!subclks) {
+               pr_err("%s: could not allocate subclks\n", __func__);

WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!onecell_data) {
+               pr_err("%s: could not allocate onecell_data\n", __func__);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:39 -08:00
Emil Medve 13c25f57d4 clk: qoriq: Fix checkpatch type ALLOC_SIZEOF_STRUCT
CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*cmux_clk)...) over kzalloc(sizeof(struct cmux_clk)...)
+       cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL);

CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*onecell_data)...) over kzalloc(sizeof(struct clk_onecell_data)...)
+       onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:39 -08:00
Emil Medve a924722597 clk: qoriq: Fix checkpatch type ALLOC_WITH_MULTIPLY
WARNING:ALLOC_WITH_MULTIPLY: Prefer kcalloc over kzalloc with multiply
+       subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:39 -08:00
Emil Medve 78f4a63e64 clk: qoriq: Fix checkpatch type PARENTHESIS_ALIGNMENT
CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+       rc = of_property_read_string_index(np, "clock-output-names",
+                       0, &clk_name);

CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+               pr_err("Could not register clock provider for node:%s\n",
+                        np->name);

CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+               rc = of_property_read_string_index(np, "clock-output-names",
+                               i, &clk_name);

CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+               pr_err("Could not register clk provider for node:%s\n",
+                        np->name);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:38 -08:00
Tang Yuantian 93a17c058f clk: ppc-corenet: rename driver to clk-qoriq
Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:12 -08:00