Commit Graph

1462 Commits

Author SHA1 Message Date
Heiko Stübner 6bc0d121a9 pinctrl: rockchip: precalculate iomux offsets
An upcoming SoC introduces an interesting quirk to iomux handling making the
calculation of the iomux register-offset harder. To keep the complexity down
when getting/setting the mux, precalculate the actual register offset at
probe-time.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:27 +02:00
Heiko Stübner fc72c923e5 pinctrl: rockchip: generalize bank-quirks
Upcoming Rockchip SoCs have additional quirks to handle. Currently they would
be handled by giving the bank a special compatible property. But the nature
of the new quirks would require a lot of them. Also as we want to move to the
separate dw_gpio driver in the future, these bank-definitions should be
extended at all.

Describing the bank quirks this way also enables us to deprecate the special
bank compatible string for bank0 on rk3188 and simplify the handling code.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:27 +02:00
Fan Wu 2243a87d90 pinctrl: avoid duplicated calling enable_pinmux_setting for a pin
What the patch does:
1. Call pinmux_disable_setting ahead of pinmux_enable_setting
  each time pinctrl_select_state is called
2. Remove the HW disable operation in pinmux_disable_setting function.
3. Remove the disable ops in struct pinmux_ops
4. Remove all the disable ops users in current code base.

Notes:
1. Great thanks for the suggestion from Linus, Tony Lindgren and
   Stephen Warren and Everyone that shared comments on this patch.
2. The patch also includes comment fixes from Stephen Warren.

The reason why we do this:
1. To avoid duplicated calling of the enable_setting operation
   without disabling operation inbetween which will let the pin
   descriptor desc->mux_usecount increase monotonously.
2. The HW pin disable operation is not useful for any of the
   existing platforms.
   And this can be used to avoid the HW glitch after using the
   item #1 modification.

In the following case, the issue can be reproduced:
1. There is a driver that need to switch pin state dynamically,
   e.g. between "sleep" and "default" state
2. The pin setting configuration in a DTS node may be like this:

  component a {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&a_grp_setting &c_grp_setting>;
	pinctrl-1 = <&b_grp_setting &c_grp_setting>;
  }

  The "c_grp_setting" config node is totally identical, maybe like
  following one:

  c_grp_setting: c_grp_setting {
	pinctrl-single,pins = <GPIO48 AF6>;
  }

3. When switching the pin state in the following official pinctrl
   sequence:
	pin = pinctrl_get();
	state = pinctrl_lookup_state(wanted_state);
	pinctrl_select_state(state);
	pinctrl_put();

Test Result:
1. The switch is completed as expected, that is: the device's
   pin configuration is changed according to the description in the
   "wanted_state" group setting
2. The "desc->mux_usecount" of the corresponding pins in "c_group"
   is increased without being decreased, because the "desc" is for
   each physical pin while the setting is for each setting node
   in the DTS.
   Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead
   of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount
   will keep increasing without any chance to be decreased.

According to the comments in the original code, only the setting,
in old state but not in new state, will be "disabled" (calling
pinmux_disable_setting), which is correct logic but not intact. We
still need consider case that the setting is in both old state
and new state. We can do this in the following two ways:

1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin
   setting" repeatedly
2. "Disable"(calling pinmux_disable_setting) the "same pin setting",
   actually two setting instances, ahead of enabling them.

Analysis:
1. The solution #2 is better because it can avoid too much
   iteration.
2. If we disable all of the settings in the old state and one of
   the setting(s) exist in the new state, the pins mux function
   change may happen when some SoC vendors defined the
   "pinctrl-single,function-off"
   in their DTS file.
   old_setting => disabled_setting => new_setting.
3. In the pinmux framework, when a pin state is switched, the
   setting in the old state should be marked as "disabled".

Conclusion:
1. To Remove the HW disabling operation to above the glitch mentioned
   above.
2. Handle the issue mentioned above by disabling all of the settings
   in old state and then enable the all of the settings in new state.

Signed-off-by: Fan Wu <fwu@marvell.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:26 +02:00
Alexander Shiyan 607af165c0 pinctrl: i.MX27: Remove nonexistent pad definitions
Pads for PB0-PB3, PC0-PC4, PE26-PE31 and PF24-PF31 does not exist on
the i.MX27 SOC. There is no reason to define them, the presence of
such definitions in the DTS files is a bug.
This patch removes these nonexistent pad definitions.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:26 +02:00
Alexander Shiyan ae23f9b1af pinctrl: i.MX27: Remove unused structure definition
struct imx27_pinctrl_private is not used in the driver.
Remove this definition.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:26 +02:00
Alexander Shiyan 4877e51ed7 pinctrl: Add i.MX1 pincontrol driver
This patch adds pincontrol driver for Freescale i.MX1 SOCs.

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:25 +02:00
Chen-Yu Tsai 0d3bafac65 pinctrl: sunxi: Fix multi bank interrupt support in gpio_to_irq
When mapping the interrupts, the gpio_to_irq function did not consider
the bank number of the gpio pin in question, only the offset or the
interrupt number in the bank. As a result, requests for interrupts in
the later banks get mapped to the first bank.

This issue was discovered while enabling mmc on the new sun8i platform.
The tablet I have uses a pin/interrupt from the second bank to do mmc
card detection. Tested on this very device with register inspection and
actual mmc card insertion/removal.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:25 +02:00
Hans de Goede d61e23e525 pinctrl: sunxi: Define enable / disable irq callbacks
Some drivers use disable_irq / enable_irq and do the work
clearing the source in another thread instead of using a threaded
interrupt handler.

The irqchip used not having irq_disable and irq_enable
callbacks in this case, will lead to unnecessary spurious
interrupts:

On a disable_irq in a chip without a handler for this, the irq
core will remember the disable, but not actually call into the
irqchip. With a level triggered interrupt (where the source has
not been cleared) this will lead to an immediate retrigger, at
which point the irq-core will mask the irq. So having an
irq_disable callback in the irqchip will save us the interrupt
firing a 2nd time for nothing.

Drivers using disable / enable_irq like this, will call
enable_irq when they finally have cleared the interrupt source,
without an enable_irq callback, this will turn into an unmask,
at which point the irq will trigger immediately because when it
was originally acked the level was still high, so the ack was
a nop.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:24 +02:00
Hans de Goede f4c51c103b pinctrl: sunxi: Properly handle level triggered gpio interrupts
For level triggered gpio interrupts we need to use handle_fasteoi_irq,
like we do with the irq-sunxi-nmi driver. This is necessary to give threaded
interrupt handlers a chance to actuall clear the source of the interrupt
(which may involve sleeping waiting for i2c / spi / mmc transfers), before
acknowledging the interrupt.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:24 +02:00
Hans de Goede fea6d8efd0 pinctrl: sunxi: Move setting of mux to irq type
With level triggered interrupt mask / unmask will get called for each
interrupt, doing the somewhat expensive mux setting on each unmask thus is
not a good idea. Instead add a request_resources callback and do it there.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:24 +02:00
Chen-Yu Tsai 578c0a8721 pinctrl: sunxi: Add IRQCHIP_SKIP_SET_WAKE flag for pinctrl irq chip
The sunxi pinctrl irq chip driver does not support wakeup at the
moment. Adding IRQCHIP_SKIP_SET_WAKE lets the irqs work with drivers
using wakeup.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:23 +02:00
Nobuhiro Iwamatsu 7d98fd3218 pinctrl: sh-pfc: r8a7791: Add HSCIF pin support
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:23 +02:00
Uwe Kleine-König 244e95a7ad pinctrl: hide CONFIG_PINMUX and CONFIG_PINCONF
These symbols are supposed to be selected by the drivers actually needing
them. The only situation where it would make sense to enable them without a
driver selecting them is when an out-of-tree pinctrl driver is used or
for compile testing.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:16 +02:00
Dan Carpenter 1419d8151b pinctrl: berlin: fix an error code in berlin_pinctrl_probe()
We are returning success here because PTR_ERR(NULL) is zero.  We should
be returning -ENODEV.

Fixes: 3de68d331c ('pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-05 01:15:35 +02:00
Linus Walleij 22763bf527 pinctrl: spear: switch plgpio to irqchip helpers
This switches the SPEAr PLGPIO driver over to using the irqchip
helpers.

As part of this effort, also get rid of the strange irq_base
calculation and failure to use d->hwirq for obtaining a local
irqchip offset.

Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Cc: spear-devel@list.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:12 +02:00
Maxime Ripard aebdc8abc9 pinctrl: sunxi: Implement multiple interrupt banks support
The A23 and A31 support multiple interrupt banks. Support it by adding a linear
domain covering all the banks. It's trickier than it should because there's an
interrupt per bank, so we have multiple interrupts using the same domain.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:12 +02:00
Maxime Ripard c11a33c15e pinctrl: sunxi: Declare the interrupt function for the A31
The primary pinctrl device has 4 interrupt banks. As usual, to be able to
generate interrupts, the pins supporting it need to be muxed to a special
function. Declare these functions in the pins array.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:12 +02:00
Maxime Ripard 8966ada2d4 pinctrl: sunxi: Declare the number of interrupt banks in the descriptor
Declare in the description structure associated to the compatible the number of
interrupt banks the device has. For now, we're not doing anything with it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:11 +02:00
Maxime Ripard 6e1c30239f pinctrl: sunxi: Add macro definition for pinctrl with more than one interrupt
The A31 and A23, unlike the other Allwinner SoCs, have several interrupts banks
and parent interrupts, while the other only have up to 32 interrupts in a
single bank and a single parent interrupt.

Start supporting it by introducing a function macro to declare irq functions
and their banks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:11 +02:00
Maxime Ripard 645ec71454 pinctrl: sunxi: Remove irq_mask_ack and use irq_ack instead
If irq_mask_ack is not defined, mask_ack_irq will call irq_mask and then
irq_ack. In order to avoid code duplication, between irq_mask_ack and irq_mask,
just declare irq_ack.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:11 +02:00
Sachin Kamat bd07894e21 pinctrl: sunxi: Fix potential null pointer dereference
kzalloc can fail. Add a null check to avoid null pointer
dereference error while accessing the pointer later.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:34:56 +02:00
Linus Torvalds bd698cf659 This is the bulk of pin control changes for the v3.16
development cycle:
 
 - Antoine Tenart made the get_group_pins() vtable entry
   optional.
 
 - Antoine also provides an entirely new driver for the
   Marvell Berlin SoC. This is unrelated to the existing
   MVEBU hardware driver and warrants its own separate
   driver.
 
 - Reflected from the GPIO subsystem there is a number of
   refactorings to make pin control drivers with gpiochips
   use the new gpiolib irqchip helpers. The following
   drivers were converted to use the new infrastructure:
 
   - ST Microelectronics STiH416 and friends
 
   - The Atmel AT91
 
   - The CSR SiRF (Prima2)
 
   - The Qualcomm MSM series
 
 - Massive improvements in the Qualcomm MSM driver from
   Bjorn Andersson, Andy Gross and Kumar Gala. Among those
   new support for the IPQ8064 and MSM8x74 SoC variants.
 
 - Support for the Freescale i.MX6 SoloX SoC variant.
 
 - Massive improvements in the Allwinner sunxi driver from
   Boris Brezillon, Maxime Ripard and Chen-Yu Tsai.
 
 - Renesas PFC updates from Laurent Pinchart, Kuninori
   Morimoto, Wolfram Sang and Magnus Damm.
 
 - Cleanups and refactorings of the nVidia Tegra driver from
   Stepgen Warren.
 
 - The Exynos driver now supports the Exynos3250 SoC.
 
 - Intel BayTrail updates from Jin Yao, Mika Westerberg.
 
 - The MVEBU driver now supports the Orion5x SoC
   variants, which is part of the effort of getting rid of
   the old Marvell kludges in arch/arm/mach-orion5x
 
 - Rockchip driver updates from Heiko Stuebner.
 
 - A ton of cleanups and janitorial patches from Axel Lin.
 
 - Some minor fixes and improvements here and there.
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Merge tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next

Pull pin control changes from Linus Walleij:
 "This is the bulk of pin control changes for the v3.16 development
  cycle:

   - Antoine Tenart made the get_group_pins() vtable entry optional.

   - Antoine also provides an entirely new driver for the Marvell Berlin
     SoC.  This is unrelated to the existing MVEBU hardware driver and
     warrants its own separate driver.

   - reflected from the GPIO subsystem there is a number of refactorings
     to make pin control drivers with gpiochips use the new gpiolib
     irqchip helpers.  The following drivers were converted to use the
     new infrastructure:
       * ST Microelectronics STiH416 and friends
       * The Atmel AT91
       * The CSR SiRF (Prima2)
       * The Qualcomm MSM series

   - massive improvements in the Qualcomm MSM driver from Bjorn
     Andersson, Andy Gross and Kumar Gala.  Among those new support for
     the IPQ8064 and MSM8x74 SoC variants.

   - support for the Freescale i.MX6 SoloX SoC variant.

   - massive improvements in the Allwinner sunxi driver from Boris
     Brezillon, Maxime Ripard and Chen-Yu Tsai.

   - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto,
     Wolfram Sang and Magnus Damm.

   - Cleanups and refactorings of the nVidia Tegra driver from Stepgen
     Warren.

   - the Exynos driver now supports the Exynos3250 SoC.

   - Intel BayTrail updates from Jin Yao, Mika Westerberg.

   - the MVEBU driver now supports the Orion5x SoC variants, which is
     part of the effort of getting rid of the old Marvell kludges in
     arch/arm/mach-orion5x

   - Rockchip driver updates from Heiko Stuebner.

   - a ton of cleanups and janitorial patches from Axel Lin.

   - some minor fixes and improvements here and there"

* tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits)
  pinctrl: sirf: fix a bad conflict resolution
  pinctrl: msm: Add more MSM8X74 pin definitions
  pinctrl: qcom: ipq8064: Fix naming convention
  pinctrl: msm: Add missing sdc1 and sdc3 groups
  pinctrl: sirf: switch to using allocated state container
  pinctrl: Enable "power-source" to be extracted from DT files
  pinctrl: sunxi: create irq/pin mapping during init
  pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy
  pinctrl: berlin: Use devm_ioremap_resource()
  pinctrl: sirf: fix typo for GPIO bank number
  pinctrl: sunxi: depend on RESET_CONTROLLER
  pinctrl: sunxi: fix pin numbers passed to register offset helpers
  pinctrl: add pinctrl driver for imx6sx
  pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs
  pinctrl: msm: switch to using generic GPIO irqchip helpers
  pinctrl: sunxi: Fix multiple registration issue
  pinctrl: sunxi: Fix recursive dependency
  pinctrl: berlin: add the BG2CD pinctrl driver
  pinctrl: berlin: add the BG2 pinctrl driver
  pinctrl: berlin: add the BG2Q pinctrl driver
  ...
2014-06-03 11:20:32 -07:00
Linus Walleij 29c7f1f53b pinctrl: sirf: fix a bad conflict resolution
Commit 294d1351ff
"pinctrl: sirf: switch to using allocated state container"
caused a build conflict due to a bad conflict resolution
when cherry-picking the patch. Fix it up.

Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-30 09:52:43 +02:00
Andy Gross 697787a16c pinctrl: msm: Add more MSM8X74 pin definitions
This patch adds pin definitiones for the MSM8x74 TLMM.
New definitions include:

BLSP devices (I2C, UART, SPI, and UIM), mi2s, gp clk,
pdm, gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif,
sdc3, sdc4, and other assorted pins.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Acked-By: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-29 10:42:59 +02:00
Kumar Gala 888bb3f9bc pinctrl: qcom: ipq8064: Fix naming convention
Drop underscore in spdif_groups to match all other groups.

Signed-off-by: Kumar Gala <galak@codeaurora.org>
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-29 10:37:43 +02:00
Bjorn Andersson f6d8812879 pinctrl: msm: Add missing sdc1 and sdc3 groups
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-28 11:02:23 +02:00
Linus Walleij 294d1351ff pinctrl: sirf: switch to using allocated state container
This rewrites the SIRF pinctrl driver to allocate a state container
for the GPIO chip, just as is done for the pin controller, and
use the gpiochip_add_pin_range() to add the range from the gpiochip
side rather than adding the range from the pinctrl side.

All resulting changes are done in order to pass around a state
container rather than refer to a static global object.

Acked-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-28 10:42:04 +02:00
Ivan T. Ivanov ca6c55189a pinctrl: Enable "power-source" to be extracted from DT files
Add "power-source" property to generic options used for DT parsing files.
This  enables drivers, which use generic pin configurations, to get the
value passed to this property.

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-28 10:16:35 +02:00
Chen-Yu Tsai d54e9a28ca pinctrl: sunxi: create irq/pin mapping during init
The irq/pin mapping is used to lookup the pin to mux to the irq
function when the irq is enabled. It is created when gpio_to_irq
is called. Creating the mapping during init allows us to map the
interrupts directly from the device tree.

Originally the IRQ to pin mapping was created when gpio_to_irq
was called with a GPIO handle. The mapping in turn is used to mux
the pin into EINT mode.

If the mapping is created during gpio_to_irq, we can't use the
interrupts directly, i.e. through the DT with "interrupts = <&pio A 4>".

Instead we'd have to use "gpios = <&pio A B>", then pass the gpio
through to gpio_to_irq.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 16:11:30 +02:00
Benoit Taine db388dfb90 pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy
This issue was reported by coccicheck using the semantic patch
at scripts/coccinelle/api/memdup.cocci

Signed-off-by: Benoit Taine <benoit.taine@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 16:06:08 +02:00
Jingoo Han 49cfabc20a pinctrl: berlin: Use devm_ioremap_resource()
Use devm_ioremap_resource() because devm_request_and_ioremap() is
obsoleted by devm_ioremap_resource().

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 16:03:24 +02:00
Barry Song 648e42e140 pinctrl: sirf: fix typo for GPIO bank number
The patch 7420d2d09b12: "pinctrl: sirf: switch driver to use gpiolib
irqchip helpers" from Apr 15, 2014, leads to the following static
checker warning:

      drivers/pinctrl/sirf/pinctrl-sirf.c:578 sirfsoc_gpio_handle_irq()
      warn: buffer overflow 'sgpio_chip.sgpio_bank' 5 <= 31

Cc: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 15:25:05 +02:00
Maxime Ripard de5af04e3e pinctrl: sunxi: depend on RESET_CONTROLLER
The A31 R_PIO driver depends on the reset framework in a mandatory way. Express
this by adding a depends on the reset framework in Kconfig

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 15:19:21 +02:00
Chen-Yu Tsai b4575c6998 pinctrl: sunxi: fix pin numbers passed to register offset helpers
The pin numbers passed to sunxi_*_reg helpers to get the correct
registers should be the pin offset for the PIO block, not the
absolute number we use that is based on the alphanumeric labels
Allwinner uses.

This patch subtracts .pin_base from the pin number passed to these
functions, so the driver accesses the correct registers.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 11:26:01 +02:00
Anson Huang 2cc140fe36 pinctrl: add pinctrl driver for imx6sx
Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core
driver.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 11:24:28 +02:00
Alexander Stein cccb0c3e6a pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs
With commit 80cc3732 (pinctrl/at91: convert driver to use gpiolib irqchip)
gpiochip_set_chained_irqchip is called for PIOC, PIOD and PIOE. The
associated GPIO chip for the IRQ chip is overwritten each time, because
they share the same hard IRQ line.
Thus if an IRQ occurs on PIOC or PIOD, gpio_irq_handler will only check on
PIOE (the assigned GPIO chip) where no event occured. Thus the IRQ will
not be cleared, retriggering the ISR.
Fix that (like done before) by only set the PIOC GPIO chip to the IRQ chip
and walk the list in the irq handler.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 11:13:10 +02:00
Linus Walleij cdcb0ab630 pinctrl: msm: switch to using generic GPIO irqchip helpers
This switches the Qualcomm MSM pin control driver over to using
the generic GPIO irqchip helpers.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Josh Cartwright <joshc@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:40:04 +02:00
Maxime Ripard ba6764d57d pinctrl: sunxi: Fix multiple registration issue
When the support for the PRCM muxer on the A31 has been added, the global
static pinctl_desc definition has been left as is. Unfortunately, this
structure is used to register the pinctrl device, and prior to this
registration, we set the name and pins field.

Since this structure is shared across instances, that means that the latest
registered pinctrl device wins in setting the name, pins and pins numbers,
which is not really a good thing.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:36:27 +02:00
Maxime Ripard 118c565a8f pinctrl: sunxi: Fix recursive dependency
Fix the following configuration error:
drivers/pinctrl/sunxi/Kconfig:3:error: recursive dependency detected!
drivers/pinctrl/sunxi/Kconfig:3:	symbol PINCTRL_SUNXI is selected by PINCTRL_SUN4I_A10
drivers/pinctrl/sunxi/Kconfig:9:	symbol PINCTRL_SUN4I_A10 default value contains PINCTRL_SUNXI

Add a new intermedia PINCTRL_SUNXI_COMMON, that superseeds the PINCTRL_SUNXI
one.

We still need to keep PINCTRL_SUNXI at the moment in order to preserve
bisectability. Indeed, during that merge window, we also introduced the
MACH_SUN* symbols. Since it's going through different trees, we can't rely on
the fact that the options will be there, while ARCH_SUNXI still select
PINCTRL_SUNXI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:35:16 +02:00
Antoine Tenart 48b6bce352 pinctrl: berlin: add the BG2CD pinctrl driver
Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:06:38 +02:00
Antoine Tenart b016d1bd05 pinctrl: berlin: add the BG2 pinctrl driver
Add the pin-controller driver for the Berlin BG2 SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:06:04 +02:00
Antoine Tenart 626eea8706 pinctrl: berlin: add the BG2Q pinctrl driver
Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:05:30 +02:00
Antoine Tenart 3de68d331c pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs
The Marvell Berlin boards have a group based pinmuxing mechanism. This
adds the core driver support. We actually do not need any information
about the pins here and only have the definition of the groups.

Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and
BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set
to mode 0:

Group	Modes	Offset Base	Offset	LSB	Bit Width
GSM12	3	sm_base		0x40	0x10	0x2

Ball	Group	Mode 0		Mode 1		Mode 2
BK4	GSM12	UART0_RX	IrDA0_RX	GPIO9
BH6	GSM12	UART0_TX	IrDA0_TX	GPIO10

So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
to set (sm_base + 0x40 + 0x10) &= ff3fffff.

As pin control registers are part of either chip control or system
control registers, that deal with a bunch of other functions we rely
on a regmap instead of exclusively remapping any resources.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:05:00 +02:00
Mika Westerberg 3ff95885ed pinctrl: baytrail: Add pull type, strength and open drain to debugfs output
In case of resolving power management or similar issues it might be useful
to have these properties included in the debugfs output.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:54 +02:00
Jin Yao 605a7bca7c pinctrl: baytrail: Register GPIO chip after chip->to_irq is set
If chip->to_irq is NULL ACPI GPIO helpers don't register GPIO event
handlers thus preventing any ACPI GPIO triggered events. Solve this by
calling gpiochip_add() after we have set up drivers chip->to_irq hook.

Signed-off-by: Jin Yao <yao.jin@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:53 +02:00
Jin Yao 20482d3279 pinctrl: baytrail: Add back Baytrail-T ACPI ID
Now that the x86 dynamic IRQ allocation problem has been resolved with
commmit 62a08ae2a5 (genirq: x86: Ensure that dynamic irq allocation does
not conflict), we can add back Baytrail-T ACPI ID to the pinctrl driver.

This makes the driver to work on Asus T100 where it is needed for several
things like ACPI GPIO events and SD card detection.

References: https://bugzilla.kernel.org/show_bug.cgi?id=68291
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Jin Yao <yao.jin@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:53 +02:00
Magnus Damm f39d8a72fe pinctrl: sh-pfc: r8a73a4: Allow Multiplatform Build
Add #ifdefs to allow r8a73a4 Multiplatform build. Needed
to enable r8a73a4 Multiplatform support.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:52 +02:00
Magnus Damm 672d323774 pinctrl: sh-pfc: sh73a0: Allow Multiplatform Build
Add #ifdefs to allow sh73a0 Multiplatform build. Needed
to enable sh73a0 Multiplatform support.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:52 +02:00
Magnus Damm b6c996a295 pinctrl: sh-pfc: r8a7740: Allow Multiplatform Build
Add #ifdefs to allow r8a7740 Multiplatform build. Needed
to enable r8a7740 Multiplatform support.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:51 +02:00
Laurent Pinchart 0e26e8dfb9 pinctrl: sh-pfc: Don't set the pinmux_irq irq field for multiplatform
In the multiplatform kernel case the IRQs associated with the PFC GPIOs
are specified through DT. The pinmux_irq irq field is thus ignored by
the code, and doesn't need to be set.

This will allow removing the mach/irq.h include from pfc-*.c files that
was required for the irq_pin() macro used to initialize the irq field.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:51 +02:00
Maxime Ripard b22116b33a pinctrl: sunxi: Enable the pinctrl Kconfig options by default
Enable the freshly introduced Kconfig options whenever their matching
architecture is enabled.

Since the Kconfig symbols for these machines are going through a different
tree, keep PINCTRL_SUNXI around for the moment to avoid breaking the defconfig.
It should be removed eventually.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:50 +02:00
Alexey Charkov 7ea456436f pinctrl: vt8500: Ensure value reg is updated when setting direction
Current code only touches the direction register when setting direction
to output, which breaks logic like

echo high > /sys/class/gpio/gpio0/direction

which is expected to also set the value. This patch also adds a call
to update the value register when setting direction to output.

Signed-off-by: Alexey Charkov <alchark@gmail.com>
Acked-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-22 23:46:10 +02:00
Heiko Stübner 1e747e59cc pinctrl: rockchip: base regmap supplied by a syscon
This allows the basic registers of the general register files to be supplied
by a syscon instead of being mapped locally.

The GRF registers contain a lot more than pinctrl functions like dma, usb-phy
and general soc control and status registers, intermixed with the iomux, pull
and drive-strength registers.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:16:13 +02:00
Heiko Stübner a658efaa85 pinctrl: rockchip: only map bank0-pull-region when pmu regmap missing
When the pmu registers are supplied through a syscon regmap we do not need
to map the registers ourself.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:15:46 +02:00
Heiko Stübner 14dee8677e pinctrl: rockchip: let pmu registers be supplied by a syscon
Currently the pmu registers containing pin pull settings on the rk3188 are mapped
locally when bank0 is instantiated. Add an alternative that can resolve the pmu
from a syscon phandle.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:15:17 +02:00
Heiko Stübner 622f32372b pinctrl: rockchip: rockchip_pinctrl in rockchip_get_bank_data
Convert rockchip_get_bank_data to use the struct rockchip_pinctrl because
later on we need to check a value from it when registering the gpio banks.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:14:46 +02:00
Heiko Stübner 751a99aba4 pinctrl: rockchip: use regmaps instead of raw mappings
This allows us to use syscons in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:14:15 +02:00
Heiko Stübner bfc7a42a0e pinctrl: rockchip: do not require 2nd register area
Deprecate secondary register area for rk3188 pulls. Instead use big enough
initial mapping of grf registers to catch all.

The now deprecated register is still supported though.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:13:44 +02:00
Linus Walleij 9dffe1d4a7 Pinctrl cleanup and reworks for 3.16
This serie of patch:
   - Moves the Allwinner pinctrl driver to a folder of its own
   - removes the sunxi-pinctrl-pins header, and split the driver into a core
     one, with all the logic, and smaller drivers, one for each SoC, that
     declare the pins, and will provide to the core the set of pins.
   - And does a few cleanups here and there.
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Merge tag 'sunxi-pinctrl-for-3.16' of https://github.com/mripard/linux into devel

Pinctrl cleanup and reworks for 3.16

This serie of patch:
  - Moves the Allwinner pinctrl driver to a folder of its own
  - removes the sunxi-pinctrl-pins header, and split the driver into a core
    one, with all the logic, and smaller drivers, one for each SoC, that
    declare the pins, and will provide to the core the set of pins.
  - And does a few cleanups here and there.
2014-05-09 08:47:16 +02:00
Maxime Ripard dc9691066f pinctrl: sunxi: Move the reset handling functions out of the core
The way that reset is handled right now is that it is made optional for every
pinctrl driver, while actually, it isn't used at all for the main pin
controllers so far, and while it's mandatory for the A31's secondary pin
controller.

Move the reset functions out of the core and in the driver, where they can be
made mandatory.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 19:57:18 -05:00
Maxime Ripard 340ba6c497 pinctrl: sunxi: Introduce per-driver Kconfig options
Add one Kconfig option for each driver. This will allow to better control which
driver is enabled, instead of having either all or nothing.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 19:41:44 -05:00
Maxime Ripard 2519859418 pinctrl: sunxi: Move Allwinner A20 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be.

This is the final step toward retiring pinctrl-sunxi-pins.h that used to define
all the pins for all the Allwinner SoCs in a single header, that would have in
turn result in having these structures in the final binary as many times as the
header was included.

We can finally remove that header, and remove all the driver part of the
pinctrl-sunxi core.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:04:49 -07:00
Maxime Ripard 16c675f989 pinctrl: sunxi: Move Allwinner A31 special pins driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:31 -07:00
Maxime Ripard 1c996176e7 pinctrl: sunxi: Move Allwinner A31 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:30 -07:00
Maxime Ripard 342cefb212 pinctrl: sunxi: Move Allwinner A13 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:29 -07:00
Maxime Ripard 0a127c1c39 pinctrl: sunxi: Move Allwinner A10s pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:29 -07:00
Maxime Ripard f2821b1ca3 pinctrl: sunxi: Move Allwinner A10 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:28 -07:00
Maxime Ripard 2284ba6b7d pinctrl: sunxi: Libraryse the driver
This will allow to have multiple drivers using the same core code, and
eventually, retire pinctrl-sunxi-pins.h

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:24 -07:00
Maxime Ripard 4409cafc1a pinctrl: sunxi: Switch to devm_ioremap_resource
The previous code was calling of_iomap, which doesn't do any resource
management, and doesn't call request_mem_region either. Use
devm_ioremap_resource that do both.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:44 -07:00
Maxime Ripard d10acc6353 pinctrl: sunxi: Replace hardcoded pin defines by a macro
We previously had an evergrowing (and exhaustive) list of the pins that could
be used on any Allwinner SoCs. These defines were then used by each pinctrl
driver to declare the list of functions for this pin. Since it's pretty much
all boilerplate, we can remove it just by a single macro.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:44 -07:00
Maxime Ripard 5f9107774f pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directory
This will allow to create numerous files without crippling the main pinctrl
directory.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:43 -07:00
Maxime Ripard 0df6846d55 pinctrl: sunxi: Drop unused structure members
The ranges and nranges were never used. Remove them.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:42 -07:00
Maxime Ripard d39bd8457f pinctrl: sunxi: Add const qualifier to the pin descriptor
The pins description structure were declared as const, but the of_device_id
data magic was losing it silently.

Make sure we have it on both sides.

And now that we're using const, we can also remove the useless cast in probe.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:02 -07:00
Andy Gross 2aa02733fb pinctrl: qcom: Correct name for pin 0
Fix copy/paste error in pinctrl_pin_desc for pin 0.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-02 15:42:52 -07:00
Thomas Petazzoni fd67f88478 pinctrl: mvebu: new driver for Orion platforms
This commit extends the pinctrl mvebu logic with a new driver to cover
Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281
variants of Orion5x, which are the three ones supported by the old
style MPP code in arch/arm/mach-orion5x/.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-24 15:09:35 +02:00
Heiko Stübner a076e2ed3f pinctrl: rockchip: implement PIN_CONFIG_OUTPUT handling
In some cases it is nice to be able to simply control a gpio output
via the PIN_CONFIG_OUTPUT option without having a driver control it.
Thus add support for it to the rockchip pinctrl driver.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 23:19:40 +02:00
Heiko Stübner dab3eba7c1 pinctrl: rockchip: return a complete config in pinconf_get
Till now pinconf_get only set the argument value into the config parameter
effectively removing the actual config param value. As other pinctrl drivers
do, it might be nicer to keep the config param intact.
Therefore construct a real pinconfig value from param and arg in pinconf_get

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 23:18:37 +02:00
Linus Walleij 7420d2d09b pinctrl: sirf: switch driver to use gpiolib irqchip helpers
This switches the SiRF pinctrl driver over to using the gpiolib
irqchip helpers simplifying some of the code.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 22:02:54 +02:00
Barry Song c5eb757ca8 pinctrl: sirf: wrap all gpio banks into one gpio_chip
all gpio banks are in one chip, that makes software clean in mapping
irq and gpio.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 22:01:31 +02:00
Linus Walleij aef95b691f pinctrl: sirf: rename inlined accessor
The sirfsoc_irqchip_to_bank() is obviously misnamed, as it is
not converting an irqchip to a bank but converts a gpiochip
to a bank so rename it sirfsoc_gpiochip_to_bank().

Acked-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 22:01:17 +02:00
Phil Edworthy 0c66c5628b sh-pfc: r8a7791: Fix definition of MOD_SEL3
There is a missing 0 entry from the MOD_SEL3 table.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 16:09:53 +02:00
Guido Piasenza 34ce57e9df sh-pfc: r8a7790: Fix definition of IPSR5
The extra entry in the table makes SCIFA0_B, and all
peripherals after it, fail.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 16:08:23 +02:00
Andy Gross b4da6573e7 pinctrl: qcom: Add definitions for IPQ8064
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm IPQ8064 platform.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 15:59:58 +02:00
Tony Lindgren 58968625c4 pinctrl: single: Clear pin interrupts enabled by bootloader
Since we set up device wake-up interrupts as pinctrl-single
interrupts, we now must use the standard request_irq and
related functions to manage them.

If the pin interrupts are enabled for some pins at boot,
the wake-up events can show up as constantly pending
at least on omaps and will hang the system unless the related
device driver clears the event at the device.

To fix this, let's clear the interrupt flags during init,
and print out a warning so the board maintainers can update
their drivers to do proper request_irq for the driver specific
wake-up events.

Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 15:56:56 +02:00
Tomasz Figa d97f5b9804 pinctrl: exynos: Add driver data for Exynos3250
This patch adds driver data (bank list and EINT layout) for Exynos3250
to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
ports. There are 23 general port groups.

Changes from v1:
- Add signed-off of sender
- Post only separated patch for pinctrl from following patchset(v1)
  : https://lkml.org/lkml/2014/4/10/286

Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 09:00:25 +02:00
Alexander Stein 47f227163a pinctrl/at91: Fix mask creation in at91_gpio_dbg_show
pin_to_mask expects a bank pin number. So do not add the chip base.

Without that patch cat /sys/kernel/debug/gpio looks like that:
GPIOs 0-31, platform/fffff200.gpio, fffff200.gpio:
[spi32766.0] GPIOfffff200.gpio5: [gpio] set
[ads7846_pendown] GPIOfffff200.gpio15: [gpio] set
[ohci_vbus] GPIOfffff200.gpio21: [gpio] set
[ohci_vbus] GPIOfffff200.gpio24: [gpio] set
[button1] GPIOfffff200.gpio28: [gpio] clear
[button2] GPIOfffff200.gpio29: [gpio] clear

GPIOs 32-63, platform/fffff400.gpio, fffff400.gpio:
[sda] GPIOfffff400.gpio4: [periph A]
[scl] GPIOfffff400.gpio5: [periph A]
[spi32766.3] GPIOfffff400.gpio11: [periph A]
[error] GPIOfffff400.gpio22: [periph A]
[run] GPIOfffff400.gpio23: [periph A]

GPIOs 64-95, platform/fffff600.gpio, fffff600.gpio:
[reset_pin] GPIOfffff600.gpio29: [periph A]

GPIOs 96-127, platform/fffff800.gpio, fffff800.gpio:
[led1] GPIOfffff800.gpio5: [periph A]
[led2] GPIOfffff800.gpio6: [periph A]
[led3] GPIOfffff800.gpio7: [periph A]
[led4] GPIOfffff800.gpio8: [periph A]

GPIOs 128-159, platform/fffffa00.gpio, fffffa00.gpio:
[button3] GPIOfffffa00.gpio10: [periph A]
[button4] GPIOfffffa00.gpio12: [periph A]

Note that every bank despite bank 0 only shows "periph A" which are
obviously used as GPIOs.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 23:45:57 +02:00
Alexander Stein 80cc37329d pinctrl/at91: convert driver to use gpiolib irqchip
This converts the AT91 pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 23:37:21 +02:00
Andrew Bresticker a73d2e30b4 pinctrl: as3722: fix handling of GPIO invert bit
The AS3722_GPIO_INV bit will always be blindly overwritten by
as3722_pinctrl_gpio_set_direction() and will be ignored when
setting the value of the GPIO in as3722_gpio_set() since the
enable_gpio_invert flag is never set.  This will cause an
initially inverted GPIO to toggle when requested as an output,
which could be problematic if, for example, the GPIO controls
a critical regulator.

Instead of setting up the enable_gpio_invert flag, just leave
the invert bit alone and check it before setting the GPIO value.

Cc: <stable@vger.kernel.org> # v3.14+
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 17:04:11 +02:00
Stephen Warren 443ac95302 pinctrl: tegra: add missing kerneldoc
The kerneldoc for struct tegra_pingroup didn't describe all of the fields
in the struct. Add some extra kerneldoc to fix that.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 16:55:41 +02:00
Stephen Warren 36e80dca9f pinctrl: tegra: print better error messages
When an attempt is made to configure an unsupported option on a pin,
print the DT property name of that option, so it's easier to debug
what the problem is.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 16:53:43 +02:00
Stephen Warren 0298fc3e1b pinctrl: tegra: reduce size of data table fields
The range of npins and function ID values is small enough to fit into a
u8. Use this type rather than unsigned to shrink the pinmux data tables.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 16:52:38 +02:00
Stephen Warren 6240d691be pinctrl: tegra: remove fsafe from data tables
The fsafe value in the pingroup data tables is only used to implement
tegra_pinctrl_disable(). The only reason this function is called is when
dynamically switching between pinmux states, i.e. when disabling the old
state before programming the new state. It's simpler to have the new
target state define the expected value of each pin (and all current DTs
do that). This also gives more flexibility, since it allows individual
boards explicit control over the "inactive" mux function for each pin,
rather than requiring it to be an SoC-specific value. Assuming this, we
can get rid of the fsafe value from the driver completely, thus saving
some more space in the driver tables.

While re-writing the content of tegra124_pingroups[], fix the indentation
to use a TAB instead of spaces.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 16:50:24 +02:00
Stephen Warren e53b797474 pinctrl: tegra: remove redundant data table fields
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel
options has the relevant HW register fields in the same register as the
mux function selection. Similarly, the drvtype option is always in the
drive register, if it is supported at all. Hence, we don't need to have
struct *_reg fields in the pin group table to define which register and
bank to use for those options. Delete this to save space in the driver's
data tables.

However, many of those options are not supported on all SoCs, or not
supported on some pingroups. We need a way to detect when they are
supported. Previously, this was indicated by setting the struct *_reg
field to -1. With the struct *_reg fields removed, we use the struct
*_bit fields for this purpose instead. The struct *_bit fields need to
be expanded from 5 to 6 bits in order to store a value outside the valid
HW bit range of 0..31.

Even without removing the struct *_reg fields, we still need to add code
to validate the struct *_bit fields, since some struct *_bit fields were
already being set to -1, without an option-specific struct *_reg field to
"guard" them. In other words, before this change, the pinmux driver might
allow some unsupported options to be written to HW.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 16:48:39 +02:00
Wolfram Sang a16b81dcbf pinctrl: pfc: r8a7790: add mux data for IIC(B) cores
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 15:39:41 +02:00
Wolfram Sang 35a493de0d pinctrl: pfc: r8a7790: add i2c0 muxing
Add the muxing for the last missing i2c rcar core. Fix the sorting for
SH_PFC_PIN_NAMED while we are here.

Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 15:38:23 +02:00
Fabio Estevam 08b519534e pinctrl: pinctrl-imx: Print the mux_mode field in hex format
With debug enabled we get better readability dumps of the mux_mode register if
we use hexadecimal format instead:

imx6sl-pinctrl 20e0000.iomuxc: MX6SL_PAD_FEC_REF_CLK: 0x10 0x0001b0a8

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 15:10:35 +02:00
Kuninori Morimoto c57a05b0eb sh-pfc: r8a7791: Add Audio pin support
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 15:09:29 +02:00
Kuninori Morimoto b664cd1f02 sh-pfc: r8a7791: Add SSI pin support
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 15:08:16 +02:00
Christian Ruppert 4c5fba3d4a pinctrl/TB10x: Fix signedness bug
In the TB10x pin database, a port index of -1 is used to indicate
unmuxed GPIO pin groups. This bug fixes a 'cast to unsigned' bug of
this value.

Thanks to Dan Carpenter for highlighting this.

CC: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 14:55:02 +02:00
Antoine Ténart b6369a8f15 pinctrl: sunxi: fix typo in module author address
According to the MODULE_AUTHOR() comments, the author name should be
"Name <email>" or just "Name". Add the missing '>'.

Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 14:53:24 +02:00
Antoine Ténart e5b3b2d9ed pinctrl: allows not to define the get_group_pins operation
When using a group only pinctrl driver, which does not have any
information on the pins it is useless to define a get_group_pins
always returning an empty list of pins.

When not using get_group_pin[1], a driver must implement it so
pins = NULL and num_pins = 0. This patch makes it the default
behaviour if not defined in the pinctrl driver when used in
pinmux enable and disable funtions and in pinctrl_groups_show.

It also adds a check in pinctrl_get_group_pins and return -EINVAL if
not defined. This function is called in the gpiolib when adding when
pingroup range. It cannot be used if no group is defined, so this seams
reasonable.

[1] get_group_pin(struct pinctrl_dev *pctldev,
		  unsigned selector,
		  const unsigned **pins,
		  unsigned *num_pins);

Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 14:47:02 +02:00
Boris BREZILLON cf2908e4ff pinctrl: sunxi: add reset control support
The A31 SoC define a reset line for the R_PIO block which needs to be
deasserted.

Try to retrieve a reset control and deassert if one was found.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:47:43 +02:00
Boris BREZILLON d9d0e1f658 pinctrl: sunxi: define A31 R_PIO pin functions
The A31 SoC provides both PL and PM pio bank through the R_PIO block.

These pins all support gpio function and can bbe assigned to system
peripherals (like TWI, P2WI, JTAG, ...)

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:45:08 +02:00
Boris BREZILLON d83c82ce7c pinctrl: sunxi: support multiple pin controller
Add support for multiple pin controller instances.

First remove the static definition of the sunxi gpio chip struct and fill
the dynamically struct instead.
Then define a new pin_base field in the sunxi_pinctrl_desc which will be
used to specify the gpiochip base pin.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:42:36 +02:00
Boris BREZILLON 0aba61787f pinctrl: sunxi: add PL and PM pin definitions
Define PL and PM pin macros.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:41:23 +02:00
Boris BREZILLON e2bddc6a7d pinctrl: sunxi: disable clk when failing to probe pin controller
Disable the clk when failing to probe the pin controller device.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:40:05 +02:00
Boris BREZILLON 6415093f7f pinctrl: sunxi: check clk_prepare_enable return value
Check the clk_prepare_enable return value to avoid false positive probe.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 13:38:35 +02:00
Maxime COQUELIN 3b02dad20f pinctrl: st: Use ARRAY_SIZE for STiH415 data
This patch completes the one that used ARRAY_SIZE for STiH407 and STiH416
for setting ninput_delays and noutput_delays fields.

Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Maxime COQUELIN a4bc1f57fd pinctrl: st: Use const qualifier when required
This patch adds const qualifier where applicable.

Reported-by: Joe Perches <joe@perches.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Axel Lin edb052c3c2 pinctrl: lantiq: Fix header file include guard
Define __PINCTRL_LANTIQ_H to prevent multiple inclusion.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Axel Lin f77329d1ed pinctrl: adi2: Statize adi_gpio_irq_domain_ops
It's only referenced in this file, make it static.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Laurent Pinchart d10046e25c pinctrl: sh-pfc: r8a7791: Split the DU sync and cde/disp groups
The DU parallel interface ODDF signal is optional, move it out of the
HSYNC/VSYNC group into a group of its down. The CDE and DISP signals are
independent, split them to two different groups.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Uwe Kleine-König fb95a94b04 pinctrl: msm8x74: make Kconfig dependency more strict
This driver is only useful on MSM8x74, so let the driver depend on
ARCH_QCOM but allow compile coverage testing.
The main benefit is that the driver isn't available to be selected for
machines that don't have the matching hardware.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Bjorn Andersson e2c802be58 pinctrl: msm: Add definitions for the APQ8064 platform
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm APQ8064 platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:35 +02:00
Bjorn Andersson 3c25381f9b pinctrl: msm: Make number of functions variable
The various pins may have different number of functions defined, so make this
number definable per pin instead of just increasing it to the largest one for
all of the platforms.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:34 +02:00
Linus Walleij 130cbe3082 pinctrl: st: use gpiolib irqchip helpers
This lets the gpiolib core handle the irqchip set-up and
chained IRQ on the primary (behind the mux) IRQ chip in
the st pinctrl driver.

Default irq type is set to level low at irqchip add time.

The v1 was sent by Linus
(https://lkml.org/lkml/2014/4/4/287).

Two changes were necessary to make it to work properly
on STiH416:
  1 - dev reference was not passed to the gpio_chip
      struct, causing a panic.
  2 - gpiochip_irqchip_add passed IRQ_TYPE_NONE as
      default type, which caused lot of warnings at
      init time. I choose IRQ_TYPE_LEVEL_LOW as default.

Cc: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Maxime COQUELIN <maxime.coquelin@st.com>
2014-04-22 08:41:34 +02:00
Linus Walleij c15c0d160c pinctrl: st: switch IRQ locking to resource callbacks
In the mass-conversion to the new irqchip callbacks, this
in-transit IRQ support was missed. Fix it.

Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Cc: Maxime COQUELIN <maxime.coquelin@st.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22 08:41:34 +02:00
Sherman Yin 7418b5cc81 pinctrl: Rename Broadcom Capri pinctrl driver
To be consistent with other Broadcom drivers, the Broadcom Capri pinctrl
driver and its related CONFIG option are renamed to bcm281xx.

Devicetree compatible string and binding documentation use
"brcm,bcm11351-pinctrl" to match the machine binding here:
Documentation/devicetree/bindings/arm/bcm/bcm11351.txt

This driver supports pinctrl on BCM11130, BCM11140, BCM11351, BCM28145
and BCM28155 SoCs.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Bjorn Andersson 48f15e94f5 pinctrl: msm: Correct interrupt code for TLMM v2
Acking interrupts are done differently between on v2 and v3, so add an extra
attribute to the pingroup struct to let the platform definitions control this.
Also make sure to start dual edge detection by detecting the rising edge.

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Linus Walleij 6888c75b24 pinctrl: nomadik: delete stray debug print
I left this in by mistake, get rid of it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Heiko Stübner c4a532dee6 pinctrl: rockchip: handle first half of rk3188-bank0 correctly
The first half of pinbank 0 only has one muxing function (as gpios) and
does not have a special mux-register.

Therefore ensure that no other mux function can be selected and also do not
write to a non-existent register.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Heiko Stübner 14797189b3 pinctrl: rockchip: add return value to rockchip_set_mux
In a following change, rockchip_set_mux gets the possibility to fail.
Therefore add a return value to it and honor error codes in functions
using rockchip_set_mux.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Beniamino Galvani 22c0d7e36f pinctrl: rockchip: fix offset of mux registers for rk3188
The correct value of .mux_offset for rk3188 seems to be 0x60
instead of 0x68.

Heiko adds:

GPIO0 only has the second two IOMUX registers:
- GRF_GPIO0C_IOMUX at 0x68
- GRF_GPIO0D_IOMUX at 0x6c
which I guess is where my mistake comes from.

It looks like there does no iomux register exist at all
for the first 16 pins.

In any case, the current number is wrong, and the 0x60
offset is the correct one, but I guess we need to
determine what the affected pins do - do they always have a
gpio mux or such?

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14 09:39:33 +02:00
Linus Torvalds 154d6f18a4 This is the bulk of GPIO changes for v3.15:
- Merged in a branch of irqchip changes from Thomas
   Gleixner: we need to have new callbacks from the
   irqchip to determine if the GPIO line will be eligible
   for IRQs, and this callback must be able to say "no".
   After some thinking I got the branch from tglx and
   have switched all current users over to use this.
 
 - Based on tglx patches, we have added some generic
   irqchip helpers in the gpiolib core. These will
   help centralize code when GPIO drivers have simple
   chained/cascaded IRQs. Drivers will still define
   their irqchip vtables, but the gpiolib core will
   take care of irqdomain set-up, mapping from local
   offsets to Linux irqs, and reserve resources by
   marking the GPIO lines for IRQs.
 
 - Initially the PL061 and Nomadik GPIO/pin control
   drivers have been switched over to use the new
   gpiochip-to-irqchip infrastructure with more
   drivers expected for the next kernel cycle. The
   factoring of just two drivers still makes it worth
   it so it is already a win.
 
 - A new driver for the Synopsys DesignWare APB GPIO
   block.
 
 - Modify the DaVinci GPIO driver to be reusable also
   for the new TI Keystone architecture.
 
 - A new driver for the LSI ZEVIO SoCs.
 
 - Delete the obsolte tnetv107x driver.
 
 - Some incremental work on GPIO descriptors: have
   gpiod_direction_output() use a logical level,
   respecting assertion polarity through ACTIVE_LOW
   flags, adding gpiod_direction_output_raw() for the
   case where you want to set that very value. Add
   gpiochip_get_desc() to fetch a GPIO descriptor from
   a specific offset on a certain chip inside driver
   code.
 
 - Switch ACPI GPIO code over to using
   gpiochip_get_desc() and get rid of gpio_to_desc().
 
 - The ACPI GPIO event handling code has been reworked
   after encountering an actual real life implementation.
 
 - Support for ACPI GPIO operation regions.
 
 - Generic GPIO chips can now be assigned labels/names
   from platform data.
 
 - We now clamp values returned from GPIO drivers to
   the boolean [0,1] range.
 
 - Some improved documentation on how to use the polarity
   flag was added.
 
 - The a large slew of incremental driver updates and
   non-critical fixes. Some targeted for stable.
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Merge tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull bulk of gpio updates from Linus Walleij:
 "A pretty big chunk of changes this time, but it has all been on
  rotation in linux-next and had some testing.  Of course there will be
  some amount of fixes on top...

   - Merged in a branch of irqchip changes from Thomas Gleixner: we need
     to have new callbacks from the irqchip to determine if the GPIO
     line will be eligible for IRQs, and this callback must be able to
     say "no".  After some thinking I got the branch from tglx and have
     switched all current users over to use this.

   - Based on tglx patches, we have added some generic irqchip helpers
     in the gpiolib core.  These will help centralize code when GPIO
     drivers have simple chained/cascaded IRQs.  Drivers will still
     define their irqchip vtables, but the gpiolib core will take care
     of irqdomain set-up, mapping from local offsets to Linux irqs, and
     reserve resources by marking the GPIO lines for IRQs.

   - Initially the PL061 and Nomadik GPIO/pin control drivers have been
     switched over to use the new gpiochip-to-irqchip infrastructure
     with more drivers expected for the next kernel cycle.  The
     factoring of just two drivers still makes it worth it so it is
     already a win.

   - A new driver for the Synopsys DesignWare APB GPIO block.

   - Modify the DaVinci GPIO driver to be reusable also for the new TI
     Keystone architecture.

   - A new driver for the LSI ZEVIO SoCs.

   - Delete the obsolte tnetv107x driver.

   - Some incremental work on GPIO descriptors: have
     gpiod_direction_output() use a logical level, respecting assertion
     polarity through ACTIVE_LOW flags, adding gpiod_direction_output_raw()
     for the case where you want to set that very value.  Add
     gpiochip_get_desc() to fetch a GPIO descriptor from a specific
     offset on a certain chip inside driver code.

   - Switch ACPI GPIO code over to using gpiochip_get_desc() and get rid
     of gpio_to_desc().

   - The ACPI GPIO event handling code has been reworked after
     encountering an actual real life implementation.

   - Support for ACPI GPIO operation regions.

   - Generic GPIO chips can now be assigned labels/names from platform
     data.

   - We now clamp values returned from GPIO drivers to the boolean [0,1]
     range.

   - Some improved documentation on how to use the polarity flag was
     added.

   - a large slew of incremental driver updates and non-critical fixes.
     Some targeted for stable"

* tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (80 commits)
  gpio: rcar: Add helper variable dev = &pdev->dev
  gpio-lynxpoint: force gpio_get() to return "1" and "0" only
  gpio: unmap gpio irqs properly
  pch_gpio: set value before enabling output direction
  gpio: moxart: Actually set output state in moxart_gpio_direction_output()
  gpio: moxart: Avoid forward declaration
  gpio: mxs: Allow for recursive enable_irq_wake() call
  gpio: samsung: Add missing "break" statement
  gpio: twl4030: Remove redundant assignment
  gpio: dwapb: correct gpio-cells in binding document
  gpio: iop: fix devm_ioremap_resource() return value checking
  pinctrl: coh901: convert driver to use gpiolib irqchip
  pinctrl: nomadik: convert driver to use gpiolib irqchip
  gpio: pl061: convert driver to use gpiolib irqchip
  gpio: add IRQ chip helpers in gpiolib
  pinctrl: nomadik: factor in platform data container
  pinctrl: nomadik: rename secondary to latent
  gpio: Driver for SYSCON-based GPIOs
  gpio: generic: Use platform_device_id->driver_data field for driver flags
  pinctrl: coh901: move irq line locking to resource callbacks
  ...
2014-04-03 16:44:15 -07:00
Linus Torvalds d64b393253 Pin control bulk changes for the v3.15 series, no new core
functionality this time, just incremental driver updates:
 
 - A large refactoring of the MVEBU (Marvell) driver.
 
 - A large refactoring of the Tegra (nVidia) driver.
 
 - GPIO interrupt including soft edges support in the
   STi driver.
 
 - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin),
   pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung),
   sunxi (AllWinner), i.MX (Freescale), Baytrail.
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Merge tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control bulk changes from Linus Walleij:
 "Pin control bulk changes for the v3.15 series, no new core
  functionality this time, just incremental driver updates:

   - A large refactoring of the MVEBU (Marvell) driver.

   - A large refactoring of the Tegra (nVidia) driver.

   - GPIO interrupt including soft edges support in the STi driver.

   - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin),
     pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi
     (AllWinner), i.MX (Freescale), Baytrail"

* tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: tegra: add some missing Tegra114 entries
  pinctrl: tegra: fix some mistakes in Tegra124
  pinctrl: msm: fix up out-of-order merge conflict
  pinctrl: st: Fix error check for of_irq_to_resource usage
  pinctrl: tegra: consistency cleanup
  pinctrl: tegra: dynamically calculate function list of groups
  pinctrl: tegra: init Tegra20/30 at module_init time
  pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays
  pinctrl: st: add pinctrl support for the STiH407 SoC
  pinctrl: st: Enhance the controller to manage unavailable registers
  pinctrl: msm: Simplify msm_config_reg() and callers
  pinctrl: msm: Remove impossible WARN_ON()s
  pinctrl: msm: Replace lookup tables with math
  pinctrl: msm: Drop OF_IRQ dependency
  pinctrl: msm: Drop unused includes
  pinctrl: msm: Check for ngpios > MAX_NR_GPIO
  pinctrl: msm: Silence recursive lockdep warning
  pinctrl: mvebu: silence WARN to dev_warn
  pinctrl: msm: drop wake_irqs bitmap
  pinctrl-baytrail: add function mux checking in gpio pin request
  ...
2014-04-01 13:10:49 -07:00
Linus Walleij 523dcce72c pinctrl: coh901: convert driver to use gpiolib irqchip
This converts the COH901 pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-26 10:31:34 +01:00
Linus Walleij e0bc34a3da pinctrl: nomadik: convert driver to use gpiolib irqchip
This converts the Nomadik pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-26 10:31:33 +01:00
Linus Walleij 8f18bcfcd2 pinctrl: nomadik: factor in platform data container
The old platform data struct is just a leftover from the times
when the driver was not probed exclusively from the device tree.
Factor this into the general state container and simplify the
probe path.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-25 09:57:07 +01:00
Linus Walleij 194e15ba00 pinctrl: nomadik: rename secondary to latent
The "secondary irq" in the nomadik pin control driver is actually
not secondary (as in: can occur any time alongside the ordinary
irq), it is a latent IRQ. It is an IRQ that has occurred when
the system was in sleep state and has been cached in a special
register flagged from the low power management unit (PRCM).

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-25 09:57:01 +01:00
Linus Walleij 8c1d50a6a7 pinctrl: coh901: move irq line locking to resource callbacks
This switches the COH901 GPIO driver over to using the
.request_resources() and .release_resources() callbacks from
the irqchip vtable and separate the calls from the .enable()
and .disable() callbacks as the latter cannot really say no
to a request, whereas the resource callbacks can.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-18 09:28:30 +01:00
Linus Walleij 57ef04288a gpio: switch drivers to use new callback
This switches all GPIO and pin control drivers with irqchips
that were using .startup() and .shutdown() callbacks to lock
GPIO lines for IRQ usage over to using the .request_resources()
and .release_resources() callbacks just introduced into the
irqchip vtable.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-18 09:28:30 +01:00
Stephen Warren 43f23a0660 pinctrl: tegra: add some missing Tegra114 entries
Add some missing pin and drive group definitions to the driver. These
are all defined in the TRM, but missing from the driver for some reason.

Fix a couple of mistakes in the drive group definitions.

Much of the diff to tegra114_groups[] is an indentation change due to one
of the new group names being long. git diff/show -w will highlight this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-14 16:32:36 +01:00
Stephen Warren 0ffdd4b61b pinctrl: tegra: fix some mistakes in Tegra124
A couple of pairs of pin group names were swapped in the table. This
caused the wrong register to be programmed. Luckily, this had little
effect, if any, since the swapped pins were likely to be programmed
identically.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-14 16:32:36 +01:00
Linus Walleij 17cdc926ec pinctrl: msm: fix up out-of-order merge conflict
Commit 051a58b462
"pinctrl: msm: Simplify msm_config_reg() and callers"
removed the local "reg" variable in the msm_config_reg()
function, but the earlier
commit ed118a5fd9
"pinctrl-msm: Support output-{high,low} configuration"
introduced a new switchclause using it.

Fix this up by removing the offending register assignment.

Reported-by: Kbuild test robot <fengguang.wu@intel.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-14 16:32:23 +01:00
Srinivas Kandagatla bcca9220b2 pinctrl: st: Fix error check for of_irq_to_resource usage
This patch fixes an error check while using of_irq_to_resource.
of_irq_to_resource returns non-zero interrupt number on success and zero
on error. The driver was using error check is wrong way.

Without this patch the driver will configure interrupt zero if there is
no interrupt specified in the node.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:53:44 +01:00
Stephen Warren 93cfb2d862 pinctrl: tegra: consistency cleanup
Fix Tegra30/114/124 pinmux drivers consistency issues.
* Sort all lists of the same object type (e.g. #defines for pins, and
  the array that defines their names) in the same order.
* Whitespace fixes.
* Consistency in layout between the 3 drivers.

These driver files were also auto-generated, which should allow us to
make e.g. the U-Boot drivers completely consistent with the kernel in
the future:-)

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:27:33 +01:00
Stephen Warren ce43625466 pinctrl: tegra: dynamically calculate function list of groups
The per-SoC data structures for Tegra pinctrl stored some information
in a redundant way. Specifically, the list of groups that each function
could be muxed onto was stored once explicitly, and also as part of the
definition of each group. Eliminate this redundancy, and calculate each
function's list of valid groups at pinctrl probe time. This removes
thousands of lines of code from the pinctrl driver and ~16K from the
vmlinux binary size, and adds only about 500uS to the boot process (on
Tegra30; newer SoCs will likely be faster still).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:23:41 +01:00
Stephen Warren edfab368c8 pinctrl: tegra: init Tegra20/30 at module_init time
The Tegra20/30 pinctrl drivers currently initializes at arch_initcall,
whereas Tegra114/124 pinctrl drivers initialize at module_init time.
Convert Tegra20/30 to work the same way as the other drivers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:22:29 +01:00
Maxime COQUELIN 88430acf38 pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays
This patch replaces the raw values with ARRAY_SIZE for assigning the
ninput_delays and noutput_delays fields of STiH416's st_pctl_data struct.

Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:18:24 +01:00
Giuseppe Cavallaro 7ce717db38 pinctrl: st: add pinctrl support for the STiH407 SoC
This patch adds the initial support for pinctrl based on H407 SoC.

Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:17:07 +01:00
Giuseppe Cavallaro 4e6a609fb7 pinctrl: st: Enhance the controller to manage unavailable registers
This patch adds a new logic inside the st pinctrl to manage
an unsupported scenario: some sysconfig are not available!

This is the case of STiH407 where, although documented, the
following registers from SYSCFG_FLASH have been removed from the SoC.

SYSTEM_CONFIG3040
   Output Enable pad control for all PIO Alternate Functions
and
SYSTEM_ CONFIG3050
   Pull Up pad control for all PIO Alternate Functions

Without managing this condition an imprecise external abort
will be detect.

To do this the patch also reviews the st_parse_syscfgs
and other routines to manipulate the registers only if
actually available.
In any case, for example the st_parse_syscfgs detected
an error condition but no action was made in the
st_pctl_probe_dt.

Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:15:34 +01:00
Stephen Boyd 051a58b462 pinctrl: msm: Simplify msm_config_reg() and callers
We don't need to check for a negative reg here because reg is
always the same and is always non-negative. Also, collapse the
switch statement down for the duplicate cases.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:29 +01:00
Stephen Boyd 1a0840ae03 pinctrl: msm: Remove impossible WARN_ON()s
All these functions are limited in what they can pass as the gpio
or irq number to whatever is setup during probe. Remove the
checks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:28 +01:00
Stephen Boyd 7cc34e2e1a pinctrl: msm: Replace lookup tables with math
We don't need to waste space with these lookup tables, just do
the math directly.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:28 +01:00
Stephen Boyd 5f2449d022 pinctrl: msm: Drop OF_IRQ dependency
This driver doesn't rely on any functionality living in
drivers/of/irq.c to compile. Drop this dependency.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:27 +01:00
Stephen Boyd af3e18f13d pinctrl: msm: Drop unused includes
These includes are unused or can be handled via forward
declarations. Remove them.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:27 +01:00
Stephen Boyd dcd278b860 pinctrl: msm: Check for ngpios > MAX_NR_GPIO
Fail the probe and print a warning if SoC specific drivers have
more GPIOs than there can be accounted for in the static bitmaps.
This should avoid silent corruption/failures in the future.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:27 +01:00
Stephen Boyd 3525f5556a pinctrl: msm: Silence recursive lockdep warning
If a driver calls enable_irq_wake() on a gpio turned interrupt
from the msm pinctrl driver we'll get a lockdep warning like so:

=============================================
[ INFO: possible recursive locking detected ]
3.14.0-rc3 #2 Not tainted
---------------------------------------------
modprobe/52 is trying to acquire lock:
 (&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88

but task is already holding lock:
 (&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88

other info that might help us debug this:
 Possible unsafe locking scenario:

       CPU0
       ----
  lock(&irq_desc_lock_class);
  lock(&irq_desc_lock_class);

 *** DEADLOCK ***

 May be due to missing lock nesting notation

4 locks held by modprobe/52:
 #0:  (&__lockdep_no_validate__){......}, at: [<c04f2864>] __driver_attach+0x48/0x98
 #1:  (&__lockdep_no_validate__){......}, at: [<c04f2874>] __driver_attach+0x58/0x98
 #2:  (&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88
 #3:  (&(&pctrl->lock)->rlock){......}, at: [<c04bb4b8>] msm_gpio_irq_set_wake+0x20/0xa8

Silence it by putting the gpios into their own lock class.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:12:19 +01:00
Sebastian Hesselbarth 3c7d563789 pinctrl: mvebu: silence WARN to dev_warn
Pinctrl will WARN on missing DT resources, which is a little bit too
noisy. Use dev_warn with FW_BUG instead.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 15:00:04 +01:00
Josh Cartwright 6aced33f49 pinctrl: msm: drop wake_irqs bitmap
Currently, the wake_irqs bitmap is used to track whether there are any
gpio's which are configured as wake irqs, and uses this to determine
whether or not to call enable_irq_wake()/disable_irq_wake() on the
summary interrupt.

However, the genirq core already handles this case, by maintaining a
'wake_count' per irq_desc, and only calling into the controlling
irq_chip when wake_count transitions 0 <-> 1.

Drop this bitmap, and unconditionally call irq_set_irq_wake() on the
summary interrupt.

Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12 14:54:28 +01:00