Commit Graph

441 Commits

Author SHA1 Message Date
Russell King 96a4d1e234 Merge branch 'pm-upstream/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm 2009-08-10 15:50:27 +01:00
Russell King f40aac940a Merge branch 'omap_fixes_31' of git://git.pwsan.com/linux-2.6 2009-08-10 14:24:18 +01:00
Russell King 7063c88c72 Merge branch 'omap-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 2009-08-10 14:23:29 +01:00
Roger Quadros 22833044fb OMAP2/3: mmc-twl4030: Free up MMC regulators while cleaning up
twl_mmc_cleanup() must free up the regulators that were
allocated by twl_mmc_late_init().
This eliminates the below error when 'omap_hsmmc' module is
repeatedly loaded and unloaded.

"sysfs: cannot create duplicate filename '/devices/platform
 /mmci-omap-hs.0/microamps_requested_vmmc'"

Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-08-10 14:49:51 +03:00
Roger Quadros dfc27b3449 OMAP3: RX51: Define TWL4030 USB transceiver in board file
Add OTG transceiver to RX51 platform data to prevent kernel NULL pointer
dereference during MUSB initialisation.

Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>
Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-08-10 14:49:51 +03:00
Sergio Aguirre 5032902c33 OMAP3: Overo: Fix smsc911x platform device resource value
Fixes a wrong setting of resource parameter list in
SMSC911x platform driver data structure for Overo case.

This fixes folowing warning when compiling for Overo board:

	warning: initialization from incompatible pointer type

Introduced since commit id:
	commit 172ef27544
	Author: Steve Sakoman <sakoman@gmail.com>
	Date:   Mon Feb 2 06:27:49 2009 +0000

	    ARM: Add SMSC911X support to Overo platform (V2)

Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-08-10 14:49:50 +03:00
Gupta, Ajay Kumar e8e2ff462d USB: musb: fix the nop registration for OMAP3EVM
OMAP3EVM uses ISP1504 phy which doesn't require any programming and
thus has to use NOP otg transceiver.

Cleanups being done:
	- Remove unwanted code in usb-musb.c file
	- Register NOP in OMAP3EVM board file using
	  usb_nop_xceiv_register().
	- Select NOP_USB_XCEIV for OMAP3EVM boards.
	- Don't enable TWL4030_USB in omap3_evm_defconfig

Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Eino-Ville Talvala <talvala@stanford.edu>
Acked-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-08-07 16:05:13 -07:00
Kevin Hilman 6fd210a9cc OMAP3: Overo: add missing pen-down GPIO definition
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:54 -07:00
Jouni Hogander 6c5f80393b OMAP3: PM: Fix wrong sequence in suspend.
Powerdomain previous state is checked after restoring new states in
suspend. This patch fixes this problem.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:54 -07:00
Kevin Hilman bcf396c480 OMAP2/3/4: UART: allow in-order port traversal
Use list_add_tail() when adding discovered UART ports.  This is so
traversal using list_for_each_entry() will traverse the list in the
order they were found.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:53 -07:00
Kevin Hilman fd455ea899 OMAP2/3/4: UART: Allow per-UART disabling wakeup for serial ports
This patch causes the OMAP uarts to honor the sysfs power/wakeup file
for IOPAD wakeups. Before the OMAP was always woken up from off mode
on a rs232 signal change.  This patch also creates a different
platform device for each serial port so that the wakeup properties can
be control per port.

By default, IOPAD wakeups are enabled for each UART.  To disable,

  # echo disabled > /sys/devices/platform/serial8250.0/power/wakeup

Where serial8250.0 can be replaced by .1, or .2 to control the other
ports.

Original idea and original patch from Russ Dill <russ.dill@gmail.com>

Cc: Russ Dill <russ.dill@gmail.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:53 -07:00
Tero Kristo 2466211e5d OMAP3: Fixed crash bug with serial + suspend
It was possible for an unhandled interrupt to occur if there was incoming
serial traffic during wakeup from suspend. This was caused by the code
in arch-arm/mach-omap2/serial.c keeping interrupt enabled all the time,
but not acking its interrupts. Applies on top of PM branch.

Use the PM begin/end hooks to ensure that the "serial idle" interrupts
are disabled during the suspend path.  Also, since begin/end hooks are
now used, use the suspend_state that is passed in the begin hook instead
of the enter hook as per the platform_suspend_ops docs.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:53 -07:00
Kevin Hilman 4789998a30 OMAP4: UART: cleanup special case IRQ handling
Streamline the OMAP4 special IRQ assignments by putting inside
normal init loop instead of having a separate loop.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:52 -07:00
Kevin Hilman 10f90ed2d7 OMAP3: PM: Do not build suspend code if SUSPEND is not enabled
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:52 -07:00
Kevin Hilman 040fed059c OMAP3: PM: prevent module wakeups from waking IVA2
By default, prevent functional wakeups from inside a module from
waking up the IVA2.  Let DSP Bridge code handle this when loaded.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:52 -07:00
Kevin Hilman 3a07ae30a0 OMAP3: PM: Clear pending PRCM reset flags on init
Any pending reset flags can prevent retention.  Ensure they are all
cleared during boot.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:52 -07:00
Kevin Hilman 3a6667acf9 OMAP3: PM: Ensure PRCM interrupts are cleared at boot
Any pending PRCM interrupts can prevent retention.  Ensure
they are cleared during boot.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:51 -07:00
Kevin Hilman 364dd47466 OMAP3: PM: CM_REGADDR macros using wrong name
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:50 -07:00
Kevin Hilman 7cc515f74d OMAP2/3: PM: make PM __init calls static
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-08-05 09:10:50 -07:00
Jaswinder Singh Rajput efda2b4c8a ARM: includecheck fix: mach-omap2/mcbsp.c
fix the following 'make includecheck' warning:

  arch/arm/mach-omap2/mcbsp.c: mach/irqs.h is included more than once.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
Acked-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-07-25 17:08:23 +01:00
Paul Walmsley 3c82e229f0 OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices.  These devices are both interconnect
initiators and targets.  Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:

    Clock usbhost_48m_fck didn't enable in 100000 tries

Two bugs are fixed by this patch.  First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond.  ES1 chips
should not wait for these clocks to enable.  So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.

Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks.  It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1].  Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.

This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].

In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.

Problem reported by Jarkko Nikula <jhnikula@gmail.com>:

    http://marc.info/?l=linux-omap&m=124306184903679&w=2

...

1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
   DSS case).

2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.

3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html


Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 20:10:36 -06:00
Paul Walmsley 3dc2197579 OMAP2 clock: 2430 I2CHS uses non-standard CM_IDLEST register
OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the CM_*CLKEN bits
are in CM_{I,F}CLKEN2_CORE [1].  Fix by implementing a custom clkops
.find_idlest function to return the correct slave IDLEST register.

...

1. OMAP2430 Multimedia Device Package-on-Package (POP) Silicon Revision 2.1
   (Rev. V) Technical Reference Manual, tables 4-99 and 4-105.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 20:10:36 -06:00
Paul Walmsley 72350b29a4 OMAP2/3 clock: split, rename omap2_wait_clock_ready()
Some OMAP2/3 hardware modules have CM_IDLEST attributes that are not
handled by the current omap2_wait_clock_ready() code.  In preparation
for patches that fix the unusual devices, rename the function
omap2_wait_clock_ready() to omap2_wait_module_ready() and split it
into three parts:

1. A clkops-specific companion clock return function (by default,
   omap2_clk_dflt_find_companion())

2. A clkops-specific CM_IDLEST register address and bit shift return
   function (by default, omap2_clk_dflt_find_idlest())

3. Code to wait for the CM to indicate that the module is ready
   (omap2_cm_wait_idlest())

Clocks can now specify their own custom find_companion() and find_idlest()
functions; used in subsequent patches.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 20:10:35 -06:00
Rajendra Nayak df56556e57 OMAP3 SDRC: Move the clk stabilization delay to the right place
The clock stabilization delay post a M2 divider change is needed
even before a SDRC interface clock re-enable and not only before
jumping back to SDRAM.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 20:10:35 -06:00
Rajendra Nayak 8ff120e530 OMAP3 SDRC: Fix freeze when scaling CORE dpll to < 83Mhz
This patch fixes a bug in the CORE dpll scaling sequence which was
errouneously clearing some bits in the SDRC DLLA CTRL register and
hence causing a freeze.  The issue was observed only on platforms
which scale CORE dpll to < 83Mhz and hence program the DLL in fixed
delay mode.

Issue reported by Limei Wang <E12499@motorola.com>, with debugging
assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish
Ghongdemath <girishsg@ti.com>.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Limei Wang <E12499@motorola.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Girish Ghongdemath <girishsg@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: updated patch description to include collaboration credits]
2009-07-24 20:10:35 -06:00
Paul Walmsley 75f251e3d0 OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on boot
Stop setting SDRC_POWER.PWDENA on boot.  There is a nasty erratum
(34xx erratum 1.150) that can cause memory corruption if PWDENA is
enabled.

Based originally on a patch from Samu P. Onkalo <samu.p.onkalo@nokia.com>.

Tested on BeagleBoard rev C2.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Samu P. Onkalo <samu.p.onkalo@nokia.com>
2009-07-24 19:44:01 -06:00
Jean Pihet 9fb97412c3 OMAP3: Setup MUX settings for SDRC CKE signals
This patches ensures the MUX settings are correct for the SDRC
CKE signals to SDRAM. This allows the self-refresh to work when
2 chip-selects are in use.

A warning is thrown away in case the initial muxing is incorrect,
in order to track faulty or old-dated bootloaders.
Note: The CONFIG_OMAP_MUX and CONFIG_OMAP_MUX_WARNINGS options
must be enabled for the mux code to have effect.

Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 19:43:25 -06:00
Jean Pihet 58cda884ec OMAP3 SDRC: add support for 2 SDRAM chip selects
Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2
SDRAM parts connected to the SDRC.

This patch adds the following:
- add a new argument of type omap_sdrc_params struct*
to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
- adapted the OMAP boards files to the new prototype of
omap2_init_common_hw
- add the SDRC 2nd CS registers offsets defines
- adapt the sram sleep code to configure the SDRC for the 2nd CS

Note: If the 2nd param to omap2_init_common_hw is NULL, then the
parameters are not programmed into the SDRC CS1 registers

Tested on 3430 SDP and Beagleboard rev C2 and B5, with
suspend/resume and frequency changes (cpufreq).

Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-07-24 19:43:25 -06:00
Adrian Hunter c8e6488f7b OMAP3: RX51: Use OneNAND sync read / write
Use OneNAND sync read / write

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-06-23 13:30:25 +03:00
Adrian Hunter 6d453e84b5 OMAP2/3: gpmc-onenand: correct use of async timings
Use async timings when sync timings are not requested.

Also ensure that OneNAND is in async mode when async
timings are used.

Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-06-23 13:30:24 +03:00
Kevin Hilman 8e25ad964a OMAP2/3: Add omap_type() for determining GP/EMU/HS
The omap_type() function is added and returns the DEVICETYPE field of
the CONTROL_STATUS register.  The result can be used for conditional
code based on whether device is GP (general purpose), EMU or
HS (high security). Also move the type defines so omap1 code
compile does not require ifdefs for sections using these defines.

This code is needed for the following fix to set the SRAM
size correctly for HS omaps.  Also at least PM and watchdog
code will need this function.

Signed-off-by: Kevin Hilman <khilman@ti.deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-06-23 13:30:23 +03:00
Roel Kluin 091a58af0b OMAP2/3: omap mailbox: platform_get_irq() error ignored
platform_get_irq may return -ENXIO. but struct omap_mbox mbox_dsp_info.irq
is unsigned, so the error was not noticed.

Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-06-23 13:30:22 +03:00
Grazvydas Ignotas 762ad3a476 OMAP2/3: mmc-twl4030: use correct controller in twl_mmc23_set_power
twl_mmc23_set_power() has MMC2 twl_mmc_controller hardcoded in it, which
breaks MMC3. Find the right controller to use instead.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2009-06-23 13:30:22 +03:00
Russell King 312cec5d09 Merge branch 'omap-clock-for-next' of git://git.pwsan.com/linux-2.6 into devel 2009-06-20 10:57:40 +01:00
Roel Kluin 2687069f3a OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons
with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1
after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success.

Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:32 -06:00
Paul Walmsley 7b7bcefa35 OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL
Correspondence with the TI OMAP hardware team indicates that
SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f.  This number
was apparently derived from process validation.  This is only used
when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than
83MHz).

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:32 -06:00
Tero Kristo 3afec6332e OMAP3: Add support for DPLL3 divisor values higher than 2
Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control.

Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
2009-06-19 19:09:32 -06:00
Paul Walmsley df14e4747a OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers
Convert omap3_sram_configure_core_dpll() to use macros rather than
magic numbers.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:32 -06:00
Paul Walmsley 4267b5d152 OMAP3 SRAM: add more comments on the SRAM code
Clean up comments and copyrights on the CORE DPLL3 M2 divider change code.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:31 -06:00
Paul Walmsley d0ba3922ae OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency.  Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:31 -06:00
Paul Walmsley c9812d042a OMAP3 clock: add a short delay when lowering CORE clk rate
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize.  Without this delay, the system is prone to random
panics upon re-entering SDRAM.

This time delay varies based on MPU frequency.  At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:31 -06:00
Paul Walmsley 2f135eaf18 OMAP3 clock: initialize SDRC timings at kernel start
On the OMAP3, initialize SDRC timings when the kernel boots.  This ensures
that the kernel is running with known, optimized SDRC timings, rather than
whatever was configured by the bootloader.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:30 -06:00
Paul Walmsley 6adb8f388e OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize
The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider.  This does not appear
to be necessary.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-19 19:09:30 -06:00
Santosh Shilimkar 934f8be7b1 ARM: OMAP4: SMP: Enable SMP support for OMAP4430
This patch enables SMP on OMAP4430 SDP platform.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-06-09 13:04:06 +05:30
Santosh Shilimkar 39e1d4c18f ARM: OMAP4: SMP: Add mpu timer support for OMAP4430
This patch adds SMP platform specific parts for local(mpu) timer support
for OMAP4430 platform. Each Cortex-a9 core has it's own local timer in the
MPU domain. These timers are not in wakeup domain.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-06-09 13:03:59 +05:30
Santosh Shilimkar 367cd31ee0 ARM: OMAP4: SMP: Add OMAP4430 SMP board files
This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430
SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC
with GIC used for interrupt handling and SCU for cache coherency.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2009-06-09 13:03:50 +05:30
Russell King 949abd84cd Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel
Conflicts:
	arch/arm/Makefile
2009-05-29 20:03:43 +01:00
Russell King 42f1d2e06a Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci into devel 2009-05-29 10:04:24 +01:00
Tony Lindgren cd07ecc828 Merge branch 'omap4' into for-next 2009-05-28 15:45:14 -07:00
Tony Lindgren 4c50d22a0c Merge branch 'omap3-boards' into for-next 2009-05-28 15:45:07 -07:00