Commit Graph

4 Commits

Author SHA1 Message Date
Aurelien BOUIN adc60298c8 ASoC: fsl_esai: Fix incorrect xDC field width of xCCR registers
The xDC field should have 5 bit width according to Reference Manual.
Thus this patch fixes it.

Signed-off-by: Aurelien BOUIN <a_bouin@yahoo.fr>
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
2014-12-30 11:29:19 +00:00
Shengjiu Wang de0d712a6d ASoC: fsl_esai: refine esai for TDM support
Original driver didn't store the number of slots, just fix the slot number
to 2, use this default number to calculate bclk and pins for TX/RX.
In this patch, add one parameter for slots, and update the calculation of
bclk and pins of TX/RX. Then driver will be compatible with slots > 2 in
TDM mode.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-08-16 17:06:15 -05:00
Xiubo Li 236014ac7a ASoC: fsl-esai: fix ESAI TDM slot setting
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-10 13:39:18 +00:00
Nicolin Chen 43d24e76b6 ASoC: fsl_esai: Add ESAI CPU DAI driver
This patch implements a device-tree-only CPU DAI driver for Freescale ESAI
controller that supports:

 - 12 channels playback and 8 channels record.
   [ Some of the inner transmitters and receivers are sharing same group of
     pins. So the maxmium 12 output or 8 input channels are only valid if
     there is no pin conflict occurring to it. ]

 - Independent (asynchronous mode) or shared (synchronous mode) transmit and
   receive sections with separate or shared internal/external clocks and frame
   syncs, operating in Master or Slave mode.
   [ Current ALSA seems not to allow CPU DAI drivers to configure DAI format
     separately for PLAYBACK and CAPTURE. So this first version only supports
     the case that uses the same DAI format for both directions. ]

 - Various DAI formats: I2S, Left-Justified, Right-Justified, DSP-A and DSP-B.

 - Programmable word length (8, 16, 20 or 24bits)

 - Flexible selection between system clock or external oscillator as input
   clock source, programmable internal clock divider and frame sync generation.

Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-01-10 12:52:15 +00:00