2 Commits

Author	SHA1	Message	Date
Weiyi Lu	f72595cf44	clk: mediatek: update clock driver of MT2712 ... According to ECO design change, 1. add new clock mux data and change some 2. add new clock gate data and clock factor data 3. change status register offset of infra subsystem Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-03-19 14:37:40 -07:00
weiyi.lu@mediatek.com	e2f744a82d	clk: mediatek: Add MT2712 clock support ... Add MT2712 clock support, include topckgen, apmixedsys, infracfg, pericfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> [sboyd@codeaurora.org: Static on top_clk_data] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2017-11-02 01:02:53 -07:00