At times where UML used the TT mode to operate it had
kind of SMP support. It never got finished nor was
stable.
Let's rip out that cruft and stop confusing developers
which do tree-wide SMP cleanups.
If someone wants SMP support UML it has do be done from scratch.
Signed-off-by: Richard Weinberger <richard@nod.at>
Before we had SKAS0 UML had two modes of operation
TT (tracing thread) and SKAS3/4 (separated kernel address space).
TT was known to be insecure and got removed a long time ago.
SKAS3/4 required a few (3 or 4) patches on the host side which never went
mainline. The last host patch is 10 years old.
With SKAS0 mode (separated kernel address space using 0 host patches),
default since 2005, SKAS3/4 is obsolete and can be removed.
Signed-off-by: Richard Weinberger <richard@nod.at>
That code is a relict from the early days of UML.
ppc support was never completed nor worked.
Let's rip it out.
Signed-off-by: Richard Weinberger <richard@nod.at>
That code is a relict from the early days of UML.
ia64 support was never completed nor worked.
Let's rip it out.
Signed-off-by: Richard Weinberger <richard@nod.at>
arch/arm64/kernel/signal.c: In function ‘handle_signal’:
arch/arm64/kernel/signal.c:290:22: warning: unused variable ‘thread’ [-Wunused-variable]
Fixes: arm64: Remove signal translation and exec_domain
Reported-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
Pull timer updates from Ingo Molnar:
"The main changes in this cycle were:
- clockevents state machine cleanups and enhancements (Viresh Kumar)
- clockevents broadcast notifier horror to state machine conversion
and related cleanups (Thomas Gleixner, Rafael J Wysocki)
- clocksource and timekeeping core updates (John Stultz)
- clocksource driver updates and fixes (Ben Dooks, Dmitry Osipenko,
Hans de Goede, Laurent Pinchart, Maxime Ripard, Xunlei Pang)
- y2038 fixes (Xunlei Pang, John Stultz)
- NMI-safe ktime_get_raw_fast() and general refactoring of the clock
code, in preparation to perf's per event clock ID support (Peter
Zijlstra)
- generic sched/clock fixes, optimizations and cleanups (Daniel
Thompson)
- clockevents cpu_down() race fix (Preeti U Murthy)"
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (94 commits)
timers/PM: Drop unnecessary braces from tick_freeze()
timers/PM: Fix up tick_unfreeze()
timekeeping: Get rid of stale comment
clockevents: Cleanup dead cpu explicitely
clockevents: Make tick handover explicit
clockevents: Remove broadcast oneshot control leftovers
sched/idle: Use explicit broadcast oneshot control function
ARM: Tegra: Use explicit broadcast oneshot control function
ARM: OMAP: Use explicit broadcast oneshot control function
intel_idle: Use explicit broadcast oneshot control function
ACPI/idle: Use explicit broadcast control function
ACPI/PAD: Use explicit broadcast oneshot control function
x86/amd/idle, clockevents: Use explicit broadcast oneshot control functions
clockevents: Provide explicit broadcast oneshot control functions
clockevents: Remove the broadcast control leftovers
ARM: OMAP: Use explicit broadcast control function
intel_idle: Use explicit broadcast control function
cpuidle: Use explicit broadcast control function
ACPI/processor: Use explicit broadcast control function
ACPI/PAD: Use explicit broadcast control function
...
Pull scheduler changes from Ingo Molnar:
"Major changes:
- Reworked CPU capacity code, for better SMP load balancing on
systems with assymetric CPUs. (Vincent Guittot, Morten Rasmussen)
- Reworked RT task SMP balancing to be push based instead of pull
based, to reduce latencies on large CPU count systems. (Steven
Rostedt)
- SCHED_DEADLINE support updates and fixes. (Juri Lelli)
- SCHED_DEADLINE task migration support during CPU hotplug. (Wanpeng Li)
- x86 mwait-idle optimizations and fixes. (Mike Galbraith, Len Brown)
- sched/numa improvements. (Rik van Riel)
- various cleanups"
* 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (28 commits)
sched/core: Drop debugging leftover trace_printk call
sched/deadline: Support DL task migration during CPU hotplug
sched/core: Check for available DL bandwidth in cpuset_cpu_inactive()
sched/deadline: Always enqueue on previous rq when dl_task_timer() fires
sched/core: Remove unused argument from init_[rt|dl]_rq()
sched/deadline: Fix rt runtime corruption when dl fails its global constraints
sched/deadline: Avoid a superfluous check
sched: Improve load balancing in the presence of idle CPUs
sched: Optimize freq invariant accounting
sched: Move CFS tasks to CPUs with higher capacity
sched: Add SD_PREFER_SIBLING for SMT level
sched: Remove unused struct sched_group_capacity::capacity_orig
sched: Replace capacity_factor by usage
sched: Calculate CPU's usage statistic and put it into struct sg_lb_stats::group_usage
sched: Add struct rq::cpu_capacity_orig
sched: Make scale_rt invariant with frequency
sched: Make sched entity usage tracking scale-invariant
sched: Remove frequency scaling from cpu_capacity
sched: Track group sched_entity usage contributions
sched: Add sched_avg::utilization_avg_contrib
...
Pull core locking changes from Ingo Molnar:
"Main changes:
- jump label asm preparatory work for PowerPC (Anton Blanchard)
- rwsem optimizations and cleanups (Davidlohr Bueso)
- mutex optimizations and cleanups (Jason Low)
- futex fix (Oleg Nesterov)
- remove broken atomicity checks from {READ,WRITE}_ONCE() (Peter
Zijlstra)"
* 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
powerpc, jump_label: Include linux/jump_label.h to get HAVE_JUMP_LABEL define
jump_label: Allow jump labels to be used in assembly
jump_label: Allow asm/jump_label.h to be included in assembly
locking/mutex: Further simplify mutex_spin_on_owner()
locking: Remove atomicy checks from {READ,WRITE}_ONCE
locking/rtmutex: Rename argument in the rt_mutex_adjust_prio_chain() documentation as well
locking/rwsem: Fix lock optimistic spinning when owner is not running
locking: Remove ACCESS_ONCE() usage
locking/rwsem: Check for active lock before bailing on spinning
locking/rwsem: Avoid deceiving lock spinners
locking/rwsem: Set lock ownership ASAP
locking/rwsem: Document barrier need when waking tasks
locking/futex: Check PF_KTHREAD rather than !p->mm to filter out kthreads
locking/mutex: Refactor mutex_spin_on_owner()
locking/mutex: In mutex_spin_on_owner(), return true when owner changes
Pull EFI update from Ingo Molnar:
"This tree includes various fixes, cleanups, a new efi=debug boot
option and EFI boot stub memory allocation optimizations"
* 'core-efi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
efi/libstub: Retrieve FDT size when loaded from UEFI config table
efi: Clean up the efi_call_phys_[prolog|epilog]() save/restore interaction
efi: Disable interrupts around EFI calls, not in the epilog/prolog calls
x86/efi: Add a "debug" option to the efi= cmdline
firmware: dmi_scan: Use direct access to static vars
firmware: dmi_scan: Use full dmi version for SMBIOS3
Almost all arches define ELF_ET_DYN_BASE as 2/3 of TASK_SIZE.
Though it seems that some architectures do this in a wrong way.
The problem is that 2*TASK_SIZE may overflow 32-bits so
the real ELF_ET_DYN_BASE becomes wrong.
Fix this overflow by dividing TASK_SIZE prior to multiplying:
(TASK_SIZE / 3 * 2)
Signed-off-by: Andrey Ryabinin <a.ryabinin@samsung.com>
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
ARM/ARM64: fixes for live migration, irqfd and ioeventfd support (enabling
vhost, too), page aging
s390: interrupt handling rework, allowing to inject all local interrupts
via new ioctl and to get/set the full local irq state for migration
and introspection. New ioctls to access memory by virtual address,
and to get/set the guest storage keys. SIMD support.
MIPS: FPU and MIPS SIMD Architecture (MSA) support. Includes some patches
from Ralf Baechle's MIPS tree.
x86: bugfixes (notably for pvclock, the others are small) and cleanups.
Another small latency improvement for the TSC deadline timer.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQEcBAABAgAGBQJVJ9vmAAoJEL/70l94x66DoMEH/R3rh8IMf4jTiWRkcqohOMPX
k1+NaSY/lCKayaSgggJ2hcQenMbQoXEOdslvaA/H0oC+VfJGK+lmU6E63eMyyhjQ
Y+Px6L85NENIzDzaVu/TIWWuhil5PvIRr3VO8cvntExRoCjuekTUmNdOgCvN2ObW
wswN2qRdPIeEj2kkulbnye+9IV4G0Ne9bvsmUdOdfSSdi6ZcV43JcvrpOZT++mKj
RrKB+3gTMZYGJXMMLBwMkdl8mK1ozriD+q0mbomT04LUyGlPwYLl4pVRDBqyksD7
KsSSybaK2E4i5R80WEljgDMkNqrCgNfg6VZe4n9Y+CfAAOToNnkMJaFEi+yuqbs=
=yu2b
-----END PGP SIGNATURE-----
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM updates from Paolo Bonzini:
"First batch of KVM changes for 4.1
The most interesting bit here is irqfd/ioeventfd support for ARM and
ARM64.
Summary:
ARM/ARM64:
fixes for live migration, irqfd and ioeventfd support (enabling
vhost, too), page aging
s390:
interrupt handling rework, allowing to inject all local interrupts
via new ioctl and to get/set the full local irq state for migration
and introspection. New ioctls to access memory by virtual address,
and to get/set the guest storage keys. SIMD support.
MIPS:
FPU and MIPS SIMD Architecture (MSA) support. Includes some
patches from Ralf Baechle's MIPS tree.
x86:
bugfixes (notably for pvclock, the others are small) and cleanups.
Another small latency improvement for the TSC deadline timer"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (146 commits)
KVM: use slowpath for cross page cached accesses
kvm: mmu: lazy collapse small sptes into large sptes
KVM: x86: Clear CR2 on VCPU reset
KVM: x86: DR0-DR3 are not clear on reset
KVM: x86: BSP in MSR_IA32_APICBASE is writable
KVM: x86: simplify kvm_apic_map
KVM: x86: avoid logical_map when it is invalid
KVM: x86: fix mixed APIC mode broadcast
KVM: x86: use MDA for interrupt matching
kvm/ppc/mpic: drop unused IRQ_testbit
KVM: nVMX: remove unnecessary double caching of MAXPHYADDR
KVM: nVMX: checks for address bits beyond MAXPHYADDR on VM-entry
KVM: x86: cache maxphyaddr CPUID leaf in struct kvm_vcpu
KVM: vmx: pass error code with internal error #2
x86: vdso: fix pvclock races with task migration
KVM: remove kvm_read_hva and kvm_read_hva_atomic
KVM: x86: optimize delivery of TSC deadline timer interrupt
KVM: x86: extract blocking logic from __vcpu_run
kvm: x86: fix x86 eflags fixed bit
KVM: s390: migrate vcpu interrupt state
...
This makes test_bit() more like its siblings *_bit() routines.
Also add some comments about the constant @nr micro-optimization
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This is the s390 version of 875ebe940d ("powerpc/smp: Wait until secondaries
are active & online").
The race described in length within the commit message is also possible on s390
and every other architecture. So fix this race on s390 as well.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Sebastian reported a crash caused by a jump label mismatch after resume.
This happens because we do not save the kernel text section during suspend
and therefore also do not restore it during resume, but use the kernel image
that restores the old system.
This means that after a suspend/resume cycle we lost all modifications done
to the kernel text section.
The reason for this is the pfn_is_nosave() function, which incorrectly
returns that read-only pages don't need to be saved. This is incorrect since
we mark the kernel text section read-only.
We still need to make sure to not save and restore pages contained within
NSS and DCSS segment.
To fix this add an extra case for the kernel text section and only save
those pages if they are not contained within an NSS segment.
Fixes the following crash (and the above bugs as well):
Jump label code mismatch at netif_receive_skb_internal+0x28/0xd0
Found: c0 04 00 00 00 00
Expected: c0 f4 00 00 00 11
New: c0 04 00 00 00 00
Kernel panic - not syncing: Corrupted kernel text
CPU: 0 PID: 9 Comm: migration/0 Not tainted 3.19.0-01975-gb1b096e70f23 #4
Call Trace:
[<0000000000113972>] show_stack+0x72/0xf0
[<000000000081f15e>] dump_stack+0x6e/0x90
[<000000000081c4e8>] panic+0x108/0x2b0
[<000000000081be64>] jump_label_bug.isra.2+0x104/0x108
[<0000000000112176>] __jump_label_transform+0x9e/0xd0
[<00000000001121e6>] __sm_arch_jump_label_transform+0x3e/0x50
[<00000000001d1136>] multi_cpu_stop+0x12e/0x170
[<00000000001d1472>] cpu_stopper_thread+0xb2/0x168
[<000000000015d2ac>] smpboot_thread_fn+0x134/0x1b0
[<0000000000158baa>] kthread+0x10a/0x110
[<0000000000824a86>] kernel_thread_starter+0x6/0xc
Reported-and-tested-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Git commit d97d929f06 ("s390: move cacheinfo sysfs to generic cacheinfo
infrastructure") removed the general-instructions-extension availability
check before the ecag instruction is executed.
Without this check this may lead to crashes on machines without this facility.
Therefore add the check again where needed.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
- don't lock lp->lock in the iss_net_timer for the call of iss_net_poll,
it will lock it itself;
- invert order of lp->lock and opened_lock acquisition in the
iss_net_open to make it consistent with iss_net_poll;
- replace spin_lock with spin_lock_bh when acquiring locks used in
iss_net_timer from non-atomic context;
- replace spin_lock_irqsave with spin_lock_bh in the iss_net_start_xmit
as the driver doesn't use lp->lock in the hard IRQ context;
- replace __SPIN_LOCK_UNLOCKED(lp.lock) with spin_lock_init, otherwise
lockdep is unhappy about using non-static key.
Cc: <stable@vger.kernel.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Old versions of binutils (before 2.23) do not yet understand the
crypto-neon-fp-armv8 fpu instructions, and an attempt to build these
files results in a build failure:
arch/arm/crypto/aes-ce-core.S:133: Error: selected processor does not support ARM mode `vld1.8 {q10-q11},[ip]!'
arch/arm/crypto/aes-ce-core.S:133: Error: bad instruction `aese.8 q0,q8'
arch/arm/crypto/aes-ce-core.S:133: Error: bad instruction `aesmc.8 q0,q0'
arch/arm/crypto/aes-ce-core.S:133: Error: bad instruction `aese.8 q0,q9'
arch/arm/crypto/aes-ce-core.S:133: Error: bad instruction `aesmc.8 q0,q0'
Since the affected versions are still in widespread use, and this breaks
'allmodconfig' builds, we should try to at least get a successful kernel
build. Unfortunately, I could not come up with a way to make the Kconfig
symbol depend on the binutils version, which would be the nicest solution.
Instead, this patch uses the 'as-instr' Kbuild macro to find out whether
the support is present in the assembler, and otherwise emits a non-fatal
warning indicating which selected modules could not be built.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: http://storage.kernelci.org/next/next-20150410/arm-allmodconfig/build.log
Fixes: 864cbeed4a ("crypto: arm - add support for SHA1 using ARMv8 Crypto Instructions")
[ard.biesheuvel:
- omit modules entirely instead of building empty ones if binutils is too old
- update commit log accordingly]
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The sha256 assembly implementation can deal with all architecture levels
from ARMv4 to ARMv7-A, but not with ARMv7-M. Enabling it in an
ARMv7-M kernel results in this build failure:
arm-linux-gnueabi-ld: error: arch/arm/crypto/sha256_glue.o: Conflicting architecture profiles M/A
arm-linux-gnueabi-ld: failed to merge target specific data of file arch/arm/crypto/sha256_glue.o
This adds a Kconfig dependency to prevent the code from being disabled
for ARMv7-M.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* pm-cpufreq:
intel_pstate: Knights Landing support
intel_pstate: remove MSR test
cpufreq: fix qoriq uniprocessor build
cpufreq: hisilicon: add acpu driver
cpufreq: powernv: Report cpu frequency throttling
cpufreq: qoriq: rename the driver
cpufreq: qoriq: Make the driver usable on all QorIQ platforms
* pm-cpuidle:
intel_idle: mark cpu id array as __initconst
intel_idle: Add support for the Airmont Core in the Cherrytrail and Braswell SOCs
intel_idle: Update support for Silvermont Core in Baytrail SOC
ARM: cpuidle: Document the code
ARM: cpuidle: Register per cpuidle device
ARM: cpuidle: Enable the ARM64 driver for both ARM32/ARM64
ARM64: cpuidle: Remove arm64 reference
ARM64: cpuidle: Rename cpu_init_idle to a common function name
ARM64: cpuidle: Replace cpu_suspend by the common ARM/ARM64 function
ARM: cpuidle: Add a cpuidle ops structure to be used for DT
ARM: cpuidle: Remove duplicate header inclusion
ksp must be 8-byte aligned.
Cc: Richard Weinberger <richard@nod.at>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
Acked-by: David S. Miller <davem@davemloft.net>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
As execution domain support is gone we can remove
signal translation from the signal code and remove
exec_domain from thread_info.
Signed-off-by: Richard Weinberger <richard@nod.at>
The RISC OS personality seems to be unused and untested for a long time.
It is doubtful whether this personality worked ever as expected.
Let's rip it out.
Signed-off-by: Richard Weinberger <richard@nod.at>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Dan Carpenter pointed out that the control flow in pt_pmu_hw_init()
is a bit messy: for example the kfree(de_attrs) is entirely
superfluous.
Another problem is the inconsistent mixing of label based and
direct return error handling.
Add modern, label based error handling instead and clean up the code
a bit as well.
Note that we'll still do a kfree(NULL) in the normal case - this does
not matter as this is an init path and kfree() returns early if it
sees a NULL.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/20150409090805.GG17605@mwanda
Signed-off-by: Ingo Molnar <mingo@kernel.org>
All places outside of core VFS that checked ->read and ->write for being NULL or
called the methods directly are gone now, so NULL {read,write} with non-NULL
{read,write}_iter will do the right thing in all cases.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
flush_old_exec() has already done that. Back on 2011 a bunch of
instances like that had been kicked out, but that hadn't taken
care of then-out-of-tree architectures, obviously, and they served
as reinfection vector...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
I don't see why we report e.g. orix_ax, which is not always
meaningful, but don't report ax, which is meaningful.
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1428671219-29341-4-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
user_64bit_mode(regs) basically checks regs->cs to point to a
64-bit segment. This check used to be unreliable here because
regs->cs was not always correct in syscalls.
Now regs->cs is always correct: in syscalls, in interrupts, in
exceptions. No need to emply heuristics here.
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1428671219-29341-3-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Yes, it is true that cx contains return address.
It's not clear why we trash it.
Stop doing that.
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1428671219-29341-2-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
After recent changes to syscall entry points,
user_regs->{cs,ss,sp} are always correct. (They used to be
undefined while in syscalls).
We can report them reliably, without guessing.
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1428671219-29341-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This problem appears to have been introduced in 2.6.29 by commit
93197a36a9 "Rewrite sysfs processor cache info code".
This caused lscpu to error out on at least e500v2 devices, eg:
error: cannot open /sys/devices/system/cpu/cpu0/cache/index2/size: No such file or directory
Some embedded powerpc systems use cache-size in DTS for the unified L2
cache size, not d-cache-size, so we need to allow for both DTS names.
Added a new CACHE_TYPE_UNIFIED_D cache_type_info structure to handle
this.
Fixes: 93197a36a9 ("powerpc: Rewrite sysfs processor cache info code")
Signed-off-by: Dave Olson <olson@cumulusnetworks.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
The hard lockup detector uses a PMU event as a periodic NMI to
detect if we are stuck (where stuck means no timer interrupts have
occurred).
Ben's rework of the ppc64 soft disable code has made ppc64 PMU
exceptions a partial NMI. They can get disabled if an external
interrupt comes in, but otherwise PMU interrupts will fire in
interrupt disabled regions.
We disable the hard lockup detector by default for a few reasons:
- It breaks userspace event based branches on POWER8.
- It is likely to produce false positives on KVM guests.
- Since PMCs can only count to 2^31, counting cycles means we might
take multiple PMU exceptions per second per hardware thread even
if our hard lockup timeout is 10 seconds.
It can be enabled via a boot option, or via procfs.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
We want to enable the hard lockup detector on ppc64, but right now
that enables the oprofile NMI timer too.
We'd prefer not to enable the oprofile NMI timer, it adds another
element to our PMU testing and it requires us to increase our
exported symbols (eg cpu_khz).
Modify the config entry for OPROFILE_NMI_TIMER to disable it on PPC64.
Signed-off-by: Anton Blanchard <anton@samba.org>
Acked-by: Robert Richter <rric@kernel.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Add missing put_cpu_var() for 24x7 requests. This went missing in
commit f34b6c7 (3.18-rc3).
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Break up the function single_24x7_request() into smaller functions.
This would later enable us to "prepare" a multi-event request
buffer and then submit a single hcall for several events.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Move the code to update an event count into a new function,
update_event_count().
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Move code that maps a perf_event to a 24x7 request buffer into a
separate function, add_event_to_24x7_request().
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
For consistency with the pmu operation ->read() and with other
pmus, rename hv_24x7_event_update() to hv_24x7_event_read().
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
To simplify/cleanup code, move the rather long printk() to a separate
function.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
The function event_24x7_request() is essentially a wrapper to the
function single_24x7_request() and can be dropped to simplify code.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Use pr_devel_ratelimited() to log error message when the 24x7 HCALL
fails. Since users specify events by their sysfs name, the HCALL should
succeed. Any errors reported by the HCALL would be of interest to the
developer, rather than the user/administrator.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Remove the 'success_expected' parameter and log the message unconditionally.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
The parameters to the 24x7 HCALL have variable number of elements in them.
Set the minimum number of such elements to 1 rather than 0 and eliminate
the temporary structures.
This would enable us to submit multiple counter requests and process
multiple results from a single HCALL (in a follow on patch).
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This change adds the OPAL interface definitions to allow Linux to read,
write and erase from system flash devices. We register platform devices
for the flash devices exported by firmware.
We clash with the existing opal_flash_init function, which is really for
the FSP flash update functionality, so we rename that initcall to
opal_flash_update_init().
A future change will add an mtd driver that uses this interface.
Changes from Joel Stanley and Jeremy Kerr.
Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This patch changes the syscall handler to doom (tabort) active
transactions when a syscall is made and return immediately without
performing the syscall.
Currently, the system call instruction automatically suspends an
active transaction which causes side effects to persist when an active
transaction fails.
This does change the kernel's behaviour, but in a way that was
documented as unsupported. It doesn't reduce functionality because
syscalls will still be performed after tsuspend. It also provides a
consistent interface and makes the behaviour of user code
substantially the same across powerpc and platforms that do not
support suspended transactions (e.g. x86 and s390).
Performance measurements using
http://ozlabs.org/~anton/junkcode/null_syscall.c
indicate the cost of a system call increases by about 0.5%.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Acked-By: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Now that we have ported the calls to iommu_init_early_dart to always
supply a pci_controller_ops struct, we can safely drop the check.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Remove shims, patch callsites to use pci_controller_ops
versions instead.
Also move back the probe mode defines, as explained in the patch
for pci_probe_mode.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This moves the Cell platform to use the pci_controller_ops
structure rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Move the installation of DMA operations out of swiotlb's subsys
initcall, and into the generic PCI controller operations struct.
These ops are installed conditionally, based on the ppc_swiotlb_enable
global. The global can be set in two places:
- swiotlb_detect_4g, which is always called at the arch initcall level
- setup_pci_atmu, which is called as part of the fsl_add_bridge and
fsl_pci_syscore_do_resume.
fsl_pci_syscore_do_resume is called late enough that any changes as a
result of that call will have no effect.
As such, if we test the global and set the operations as part of
fsl_add_bridge, after the call to setup_pci_atmu, we can be confident
that it will cover all the PCI implementations affected by the changes
to dma-swiotlb.c.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This moves the Maple platform to use the pci_controller_ops
structure rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This moves the PaSemi platform to use the pci_controller_ops
structure rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This moves the PowerNV platform to use the pci_controller_ops
structure rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This moves the pSeries platform to use the pci_controller_ops structure,
rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This moves the Power Mac platform to use the pci_controller_ops
structure rather than ppc_md for PCI controller operations.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
If a pci_controller_ops struct is provided to iommu_init_early_dart,
populate that with the DMA setup ops, rather than ppc_md. If NULL is
provided, populate ppc_md as before.
This also patches the call sites for Maple and Power Mac to pass
NULL, so existing behaviour is preserved.
The benefit of making this optional is that it means we don't have
to change dart, Maple and Power Mac over to the controller_ops
system in one fell swoop.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Add pci_controller_ops.reset_secondary_bus,
shadowing ppc_md.pcibios_reset_secondary_bus.
Add a shim, and changes the callsites to use the shim.
Use pcibios_reset_secondary_bus_shim, as both
pcibios_reset_secondary_bus and pci_reset_secondary_bus
are already taken.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Add pci_controller_ops.window_alignment,
shadowing ppc_md.pcibios_window_alignment.
Add a shim, and changes the callsites to use the shim.
Here, we use pci_window_alignment, as pcibios_window_alignment is
already taken.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Add pci_controller_ops.enable_device_hook,
shadowing ppc_md.pcibios_enable_device_hook.
Add a shim, and changes the callsites to use the shim.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Add pci_controller_ops.probe_mode, shadowing ppc_md.pci_probe_mode.
Add a shim, and changes the callsites to use the shim.
We also need to move the probe mode defines to pci-bridge.h from pci.h.
They are required by the shim in order to return a sensible default.
Previously, the were defined in pci.h, but pci.h includes pci-bridge.h
before the relevant #defines. This means the definitions are absent
if pci.h is included before pci-bridge.h. This occurs in some drivers.
So, move the definitons now, and move them back when we remove the shim.
Anything that wants the defines would have had to include pci.h, and
since pci.h includes pci-bridge.h, nothing will lose access to the
defines.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Add pci_controller_ops.dma_bus_setup, shadowing ppc_md.pci_dma_bus_setup.
Add a shim, and changes the callsites to use the shim.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Introduces the pci_controller_ops structure.
Add pci_controller_ops.dma_dev_setup, shadowing ppc_md.pci_dma_dev_setup.
Add a shim, and change the callsites to use the shim.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
pcibios_enable_device_hook returned an int. Every implementation
returned either -EINVAL or 0. The return value wasn't propagated by
the caller: any non-zero return value caused pcibios_enable_device
to return -EINVAL itself. Therefore, make the hook return a bool.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Previously, find_and_init_phbs() was used in both PowerNV and pSeries
setup. However, since RTAS support has been dropped from PowerNV, we
can move it into a platform-specific file.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
- Purge the gic_arch_extn hacks and abuse by using the new stacked domains
NOTE: Due to the nature of these changes, patches crossing subsystems have
been kept together in their own branches.
- tegra
- Handle the LIC properly
- omap
- Convert crossbar to stacked domains
- kill arm,routable-irqs in GIC binding
- exynos
- Convert PMU wakeup to stacked domains
- shmobile, ux500, zynq (irq_set_wake branch)
- Switch from abusing gic_arch_extn to using gic_set_irqchip_flags
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJVKFhRAAoJEP45WPkGe8ZnYFcP/iBznjkMYG+OUwrxo7G4rTyu
JYj0dmg/D76ewFsxWFv24II9V+KJaqrEtFTHH4MVbeEbbrDIx7Am0i/Ip6rDRgxS
7Q/jGic8etfPGV8gW6x38zbTHOl1rfqQtoHcqBH5FnLITuMAuHPa51jpwhMik4ri
AbMwb6Whep6tEsxiEjspPxXWphEZoXluOkRjPLokTwuifo4rEo7bqU8WMizzSW5g
xEjf8eUvBYIMTA40FBQWHQwxf1jRySSW2A9u5JgT1ccZHoajEyDgQr22KUHpCAWU
hlZ/8uTqCUeecDQKFPr4zXhq9mbEVZ7lld5Gl82cxY6aI3Xj/bUI3tSYubPWEgx6
0VhbmvjqKPiFfdCrLq5ZTY5UHmW8khdttdycIPNz9LmUDVgIzJpmpAW+oyG7BN/N
QgGF4lzaN49mHQmjtXGfwY3iJTadxyVaWoZTBinjw8LyxpzUO/MNQGLumsxEtkxN
Nbbsc2k+ERpSx40ospB1WOslAzMsNi6eLwqLRfjGGfSYK1P6Mm7FhansJm08p1/D
8h6ymqA4heZrYdI1vrfuy7QuEqQgnVUf0TDTHxX+aNGrHnBSsPTTfYHBOHXUh4Cr
Ox3yLECAhWle4VlgInu3XLRmuUiYGk4JV4nbZUjpZvIaOZV4gLArcsQU7C/KTDT8
CqrybDOIxFkIbxfU+EE0
=IPgJ
-----END PGP SIGNATURE-----
Merge tag 'irqchip-core-4.1-3' of git://git.infradead.org/users/jcooper/linux into irq/core
irqchip core change for v4.1 (round 3) from Jason Cooper
Purge the gic_arch_extn hacks and abuse by using the new stacked domains
NOTE: Due to the nature of these changes, patches crossing subsystems have
been kept together in their own branches.
- tegra
- Handle the LIC properly
- omap
- Convert crossbar to stacked domains
- kill arm,routable-irqs in GIC binding
- exynos
- Convert PMU wakeup to stacked domains
- shmobile, ux500, zynq (irq_set_wake branch)
- Switch from abusing gic_arch_extn to using gic_set_irqchip_flags
Commit 32098ec7bc ("MIPS: Makefile: Move the ASEs checks after
setting the core's CFLAGS") re-arranged the MIPS ASE detection code
and also added the current cflags to the detection logic. However,
this introduced a few bugs. First of all, the mips-cflags should not
be quoted since that ends up being passed as a string to subsequent
commands leading to broken detection from the cc-option-* tools.
Moreover, in order to avoid duplicating the cflags-y because of how
cc-option works, we rework the logic so we pass only those cflags which
are needed by the selected ASE. Finally, fix some typos resulting in MSA
not being detected correctly.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: Commit 32098ec7bc ("MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS")
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9661/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Set good default FPU flags (FR0) for O32 binaries similar to what the
kernel does for the N64/N32 ones. This also fixes a regression
introduced in commit 46490b5725 ("MIPS: kernel: elf: Improve the
overall ABI and FPU mode checks") when MIPS_O32_FP64_SUPPORT is
disabled. In that case, the mips_set_personality_fp() did not set the
FPU mode at all because it assumed that the FPU mode was already set
properly. That led to O32 userland problems.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reported-by: Mans Rullgard <mans@mansr.com>
Fixes: 46490b5725 ("MIPS: kernel: elf: Improve the overall ABI and FPU mode checks")
Tested-by: Mans Rullgard <mans@mansr.com>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/9344/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Since the day of adding this code it was broken. We were iterating over
a wrong array and checking for wrong NVRAM entry.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/9654/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
A 64-bit build for Malta produces far too many build problems
when SMP/CPS is selected. Moreover, there is currently no 64-bit
product with SMP/CPS so we disable SMP/CPS when building for
64-bit until it is properly supported.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8573/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We found that TLB mismatch not only happens after kernel resume, but
also happens during snapshot restore. So move it to the beginning of
swsusp_arch_suspend().
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: <stable@vger.kernel.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9621/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The lose_fpu() function only disables the FPU in CP0_Status.CU1 if the
FPU is in use and MSA isn't enabled.
This isn't necessarily a problem because KSTK_STATUS(current), the
version of CP0_Status stored on the kernel stack on entry from user
mode, does always get updated and gets restored when returning to user
mode, but I don't think it was intended, and it is inconsistent with the
case of only the FPU being in use. Sometimes leaving the FPU enabled may
also mask kernel bugs where FPU operations are executed when the FPU
might not be enabled.
So lets disable the FPU in the MSA case too.
Fixes: 33c771ba5c ("MIPS: save/disable MSA in lose_fpu")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9323/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
A driver was added in commit 5433acd81e ("MIPS: ralink: add illegal access
driver") without the Kconfig section being added. Fix this by adding the symbol
to the Kconfig file.
Signed-off-by: John Crispin <blogic@openwrt.org>
Reported-by: Paul Bolle <pebolle@tiscali.nl>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9299/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
A wrong symbol is referenced by commit 187c26ddf0 ("MIPS: ralink: add rt2880
pci driver"). Fix this by changing it to the correct symbol.
Signed-off-by: John Crispin <blogic@openwrt.org>
Reported-by: Paul Bolle <pebolle@tiscali.nl>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9298/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
memsize denotes the amount of RAM we can access from kseg{0,1} and
that should be up to 256M. In case the bootloader reports a value
higher than that (perhaps reporting all the available RAM) it's best
if we fix it ourselves and just warn the user about that. This is
usually a problem with the bootloader and/or its environment.
[ralf@linux-mips.org: Remove useless parens as suggested bei Sergei.
Reformat long pr_warn statement to fit into 80 column limit.]
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9362/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This is no longer needed with the fixed, new and improved definition
of cpu_has_mips_r2_exec_hazard in <asm/cpu-features.h>.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Returns a non-zero value if the current processor implementation requires
an IHB instruction to deal with an instruction hazard as per MIPS R2
architecture specification, zero otherwise.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit 6ebb496ffc7e("MIPS: kernel: entry.S: Add MIPS R6 related
definitions") added the MIPSR6 definition but it did not update the
ISA level of the actual assembly code so a pre-MIPSR6 jr.hb instruction
was generated instead. Fix this by using the MISP_ISA_LEVEL_RAW macro.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: 6ebb496ffc7e("MIPS: kernel: entry.S: Add MIPS R6 related definitions")
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9386/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction
with "addiu") replaced the "sub" instruction with addiu but it did
not update the immediate value in the R10000_LLSC_WAR case.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu"")
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9385/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll
functions") added support for MIPS R6 cache flushes but it used the
wrong base address register to perform the flushes so the same lines
were flushed over and over. Moreover, replace the "addiu" instructions
with LONG_ADDIU so the correct base address is calculated for 64-bit
cores.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions")
Cc: linux-mips@linux-mips.org
Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9384/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit b0a668fb20 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator
for MIPS R6") added the mips r2-to-r6 emulator so an R2 userland can be
executed on R6 kernels. This needed both build time and runtime support.
The runtime support needed the "mipsr2emu" kernel parameter instead of
the "mipsr2emul" listed in the Kconfig help message.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: b0a668fb20 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6")
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9504/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
When emulating a regular lh/lw/lhu/sh/sw we need to use the appropriate
instruction if we are in EVA mode. This is necessary for userspace
applications which trigger alignment exceptions. In such case, the
userspace load/store instruction needs to be emulated with the correct
eva/non-eva instruction by the kernel emulator.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: c1771216ab ("MIPS: kernel: unaligned: Handle unaligned accesses for EVA")
Cc: <stable@vger.kernel.org> # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9503/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
It's best to surround such complex macros with do {} while statements
so they can appear as independent logical blocks when used within other
control blocks.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9502/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit c1771216ab ("MIPS: kernel: unaligned: Handle unaligned
accesses for EVA") allowed unaligned accesses to be emulated for
EVA. However, when emulating regular load/store unaligned accesses,
we need to use the appropriate "address space" instructions for that.
Previously, an unaligned load/store instruction in kernel space would
have used the corresponding EVA instructions to emulate it which led to
segmentation faults because of the address translation that happens
with EVA instructions. This is now fixed by using the EVA instruction
only when emulating EVA unaligned accesses.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: c1771216ab ("MIPS: kernel: unaligned: Handle unaligned accesses for EVA")
Cc: <stable@vger.kernel.org> # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9501/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Introduce new macros for kernel load/store variants which will be
used to perform regular kernel space load/store operations in EVA
mode.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9500/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Update to the SATA PHY initialization. This is needed for SATA detection
to succeed in all configurations.
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8886/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fix PCI interrupt mapping for DSR1000N. This will get the PCI slot
interrupts working. The mapping is based on D-Link GPL tarball.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9593/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
udelay() in PCI/PCIe read/write callbacks cause 30ms IRQ latency on Octeon
platforms because these operations are called from PCI_OP_READ() and
PCI_OP_WRITE() under raw_spin_lock_irqsave().
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Cc: linux-mips@linux-mips.org
Cc: David Daney <ddaney@cavium.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Masanari Iida <standby24x7@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Mathias <mathias.rulf@nokia.com>
Patchwork: https://patchwork.linux-mips.org/patch/9576/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This removes all the boilerplate from the existing implementation,
and replaces it with calls into the base layer. It also changes the
prototypes of the core asm functions to be compatible with the base
prototype
void (sha512_block_fn)(struct sha256_state *sst, u8 const *src, int blocks)
so that they can be passed to the base layer directly.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This removes all the boilerplate from the existing implementation,
and replaces it with calls into the base layer. It also changes the
prototypes of the core asm functions to be compatible with the base
prototype
void (sha256_block_fn)(struct sha256_state *sst, u8 const *src, int blocks)
so that they can be passed to the base layer directly.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This removes all the boilerplate from the existing implementation,
and replaces it with calls into the base layer.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This removes all the boilerplate from the existing implementation,
and replaces it with calls into the base layer.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This removes all the boilerplate from the existing implementation,
and replaces it with calls into the base layer.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This removes all the boilerplate from the existing implementation,
and replaces it with calls into the base layer.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This removes all the boilerplate from the existing implementation,
and replaces it with calls into the base layer.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This removes all the boilerplate from the existing implementation,
and replaces it with calls into the base layer.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This removes all the boilerplate from the existing implementation,
and replaces it with calls into the base layer.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This removes all the boilerplate from the existing implementation,
and replaces it with calls into the base layer.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
============
*) Add driver for USB PHYs on sun9i
*) Add driver for USB PHY on dm816x
*) Modified exynos5-usbdrd driver to add support for Exynos5433 SoC
Fixes
=====
*) Fix power_on/power_off failure paths in some drivers
*) Make miphy365x use generic PHY type constants
*) Fix build errors due to missing export symbols in qcom-ufs driver
*) Make all the functions return proper error values
Cleanups
========
*) use PTR_ERR_OR_ZERO to simplify code
*) use devm_kcalloc instead of devm_kzalloc with multiply
*) remove un-necessary ifdef CONFIG_OF
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJVHrrMAAoJEA5ceFyATYLZV8kP/074teM4HZMAqmUVRG+nRr8b
Eb8QYOzpnazUKtUovMYePzLjIZ3kvlMepSVVZiZqP6Uc2s6bnhTUN758HZBTdMVO
Cer63lcp5eM6yBSIL4kNo3+18ikql3LJK9kQZoLGszZmVJzwwqhL/cWxl8+WfZ+P
U71ciL07xmQD1c1GbRsuDBykaDKnf4M9HVUzP9w/pFANKYWWHdR3bj53kz9W7bGm
gF/6wVFfxkknPfQjlqo9VUoSPN3P+WIcoM2rPG1b1u2adAAKFSYvXX2eJKWZF6Cz
L9IZn1bTB0tMkrbswpMRqPtKjfmGyi1Acx8jt8WVA5pjNZ4K2P+9T7vsWifEnYa/
BDYdJJRzZSL89m9zwEFvLF490pTJrk33eFbqzHDGmDcdtj8KY8XZ9Fp5R2Lmj26s
mtST0Pi+j9SGg95KZBcXd2l1EJmdDutEYy7LgVvkLk4IFPfOyaAFEhSNW+Qi+Lh9
SkDqbZUrk9ZxzsWqYJW5LVbQlscJ2NzQuf5AgkrXsufXO0B8RAV5bt0f88ENmQsJ
rbbbWIb/ljT6YbZqT8z2X8T0PNZBknSfepb5LO5QAZMMJJm2202TondsISytvC9U
fS5sBIDzuiiMtOA9FwA5Yl1bPWq6QY4OwqIMX3LAs10ylJhbuqJ7nK5qH3O4bpk+
DzOCd1oLJhXjnOXIujz2
=0gB+
-----END PGP SIGNATURE-----
Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next
Kishon writes:
New Features
============
*) Add driver for USB PHYs on sun9i
*) Add driver for USB PHY on dm816x
*) Modified exynos5-usbdrd driver to add support for Exynos5433 SoC
Fixes
=====
*) Fix power_on/power_off failure paths in some drivers
*) Make miphy365x use generic PHY type constants
*) Fix build errors due to missing export symbols in qcom-ufs driver
*) Make all the functions return proper error values
Cleanups
========
*) use PTR_ERR_OR_ZERO to simplify code
*) use devm_kcalloc instead of devm_kzalloc with multiply
*) remove un-necessary ifdef CONFIG_OF
smp_ops->probe() is currently supposed to return the number of cpus in
the system.
The last actual usage of the value was removed in May 2007 in e147ec8f18
"[POWERPC] Simplify smp_space_timers". We still passed the value around
until June 2010 when even that was finally removed in c1aa687d49
"powerpc: Clean up obsolete code relating to decrementer and timebase".
So drop that requirement, probe() now returns void, and update all
implementations.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
The patch to add it_page_shift incorrectly changed the increment of
uaddr to use it_page_shift, rather then (1 << it_page_shift).
This broke booting on at least some Cell blades, as the iommu was
basically non-functional.
Fixes: 3a553170d3 ("powerpc/iommu: Add it_page_shift field to determine iommu page size")
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
The conversion from __get_cpu_var() to this_cpu_ptr() in iic_setup_cpu()
is wrong. It causes an oops at boot.
We need the per-cpu address of struct cpu_iic, not cpu_iic.regs->prio.
Sparse noticed this, because we pass a non-iomem pointer to out_be64(),
but we obviously don't check the sparse results often enough.
Fixes: 69111bac42 ("powerpc: Replace __get_cpu_var uses")
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
We get way too many bug reports that say "the kernel is hung in
prom_init", which stems from the fact that the last piece of output
people see is "returning from prom_init".
The kernel is almost never hung in prom_init(), it's just that it's
crashed somewhere after prom_init() but prior to the console coming up.
The existing message should give a clue to that, ie. "returning from"
indicates that prom_init() has finished, but it doesn't seem to work.
Let's try something different.
This prints:
Quiescing Open Firmware ...
Booting Linux via __start() ...
Which hopefully makes it clear that prom_init() is not the problem, and
although __start() probably isn't either, it's at least the right place
to begin looking.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Wistfully-Acked-by: Jeremy Kerr <jk@ozlabs.org>
We have a powerpc specific global called mem_init_done which is "set on
boot once kmalloc can be called".
But that's not *quite* true. We set it at the bottom of mem_init(), and
rely on the fact that mm_init() calls kmem_cache_init() immediately
after that, and nothing is running in parallel.
So replace it with the generic and 100% correct slab_is_available().
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Both ARM946 and ARM940 setup functions were corrupting r1 and r2,
which is not permissible - these are used to carry the machine ID
and boot data into the kernel, and must be preserved.
The code responsible for this was the same in both files: they were
using the registers to generate a protection region register value.
Fix this by turning this process into a macro, and using that macro
in both these files with an alternative register allocation. r0,
r3 and r7 can be used for temporary values here.
Reported-by: Alex Dumitrache <broscutamaker@gmail.com>
Tested-by: Georg Hofstetter <g3gg0.de@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Update the check for UV2000/3000. Note when the HUB is not recognized.
Signed-off-by: Mike Travis <travis@sgi.com>
Acked-by: Hedi Berriche <hedi@sgi.com>
Acked-by: Dimitri Sivanich <sivanich@sgi.com>
Link: http://lkml.kernel.org/r/20150409182629.267239403@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Fix a bug in the OEM check function that determines if the
system is a UV system and the BIOS is compatible with the
kernel's UV apic driver. This prevents some possibly obscure
panics and guards the system against being started on SGI
hardware that does not have the required kernel support.
Signed-off-by: Mike Travis <travis@sgi.com>
Acked-by: Hedi Berriche <hedi@sgi.com>
Acked-by: Dimitri Sivanich <sivanich@sgi.com>
Link: http://lkml.kernel.org/r/20150409182629.112998930@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Optimize the first "SGI" OEM check to return faster if the
system is not an SGI or UV system.
Signed-off-by: Mike Travis <travis@sgi.com>
Acked-by: Hedi Berriche <hedi@sgi.com>
Acked-by: Dimitri Sivanich <sivanich@sgi.com>
Link: http://lkml.kernel.org/r/20150409182628.952357922@asylum.americas.sgi.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Commit 779c88c94c ("ARM: 8321/1: asm-generic: introduce .text.fixup
input section") introduced a new .text.fixup section which is merged
with .text at link time. This causes xtensa builds to fail with lots
of error messages similar to the following.
lib/lib.a(kobject.o): In function `kobject_create':
(.text+0x498): dangerous relocation: l32r: literal placed after use:
(.literal+0x150)
Linker script transformation needs to be updated to detect and handle
the new section.
Fixes: 779c88c94c ("ARM: 8321/1: asm-generic: introduce .text.fixup
input section")
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Chris Zankel <chris@zankel.net>
Remove the end address checking for flushda function. We need to flush
each address line for flushda instruction, from start to end address.
This is because flushda instruction only flush the cache if tag and line
fields are matched.
Change to use ldwio instruction (bypass cache) to load the instruction
that causing trap. Our interest is the actual instruction that executed
by the processor, this should be uncached.
Note, EA address might be an userspace cached address.
Signed-off-by: Ley Foon Tan <lftan@altera.com>
Enumeration
- Don't look for ACPI hotplug parameters if ACPI is disabled (Bjorn Helgaas)
Resource management
- Revert "sparc/PCI: Clip bridge windows to fit in upstream windows" (Bjorn Helgaas)
AER
- Avoid info leak in __print_tlp_header() (Rasmus Villemoes)
PCI device hotplug
- Add missing curly braces in cpci_configure_slot() (Dan Carpenter)
ST Microelectronics SPEAr13xx host bridge driver
- Drop __initdata from spear13xx_pcie_driver (Matwey V. Kornilov)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVJnuIAAoJEFmIoMA60/r89g8P/RsbbDKnun99pmmNICEFfsbN
sgKcFl8/Z1YTqyxN8idD7COsGR/XYc0StL2aHcUNqbXA5RNFZFBRoMyA4RyN8+wK
S28OD+1LB8WFg4W95yif0qoSXUmMA5W43FoZ62qlzYVADeaBN0bmO2iZcSRtbFdx
tBBxRBWzr123RZ3ShZW6NQaf7Jdwo6VH6V69C30VZp748Uxz/Sn9U6f2IAwKPM2u
hmhKCdCLnxQeiQp/0EfLPGlJk9T8WVjjicCj+WrM62RL2G0EnUb3YfXSJZSQ7Qa7
lgWbMZ8Ec4shmRsF6tGsl8KQ6bUgKj335M5AVcjiiKUvad60xf3bIxkVBt54heZR
GtbxnbnwHy10NAyRfKrsU0MvNJX4OeLX1WesPAZBy8z4anh1WBtaMAgalycbr4wG
AswVOpyc6H38b0n2gLXrTF06Zz7CD1ie/U0wTEYBJ4uIj9S5Qa10ltNsTagWq78e
JBGjcwRTyCtM0nVxvOu1b75RZAdHKlU+rwKkm3yCEwXPNrhkWZbtT5e5bZLqiWCB
xRSnZaPGTl//dV8FbhjHEx8g7ptAc3FxPuAWx2Z4ZcxDyLSXwpNzJ2yBjZaIDWfD
+j1X9hVkETatJn0fwxXepktzuQW4RZeGn06a21awbK24Q5dTNA21pGvrXhxB2gGh
YrXZthcsP06K8C7pV4n0
=ituX
-----END PGP SIGNATURE-----
Merge tag 'pci-v4.0-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI fixes from Bjorn Helgaas:
"Here are some fixes for v4.0. I apologize for how late they are. We
were hoping for some better fixes, but couldn't get them polished in
time. These fix:
- a Xen domU oops with PCI passthrough devices
- a sparc T5 boot failure
- a STM SPEAr13xx crash (use after initdata freed)
- a cpcihp hotplug driver thinko
- an AER thinko that printed stack junk
Details:
Enumeration
- Don't look for ACPI hotplug parameters if ACPI is disabled (Bjorn Helgaas)
Resource management
- Revert "sparc/PCI: Clip bridge windows to fit in upstream windows" (Bjorn Helgaas)
AER
- Avoid info leak in __print_tlp_header() (Rasmus Villemoes)
PCI device hotplug
- Add missing curly braces in cpci_configure_slot() (Dan Carpenter)
ST Microelectronics SPEAr13xx host bridge driver
- Drop __initdata from spear13xx_pcie_driver (Matwey V. Kornilov)
* tag 'pci-v4.0-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
Revert "sparc/PCI: Clip bridge windows to fit in upstream windows"
PCI: Don't look for ACPI hotplug parameters if ACPI is disabled
PCI: cpcihp: Add missing curly braces in cpci_configure_slot()
PCI/AER: Avoid info leak in __print_tlp_header()
PCI: spear: Drop __initdata from spear13xx_pcie_driver
The comment line regarding IOMMU_INIT and IOMMU_INIT_FINISH
macros is incorrect:
"The standard vs the _FINISH differs in that the _FINISH variant
will continue detecting other IOMMUs in the call list..."
It should be "..the *standard* variant will continue
detecting..."
Fix that. Also, make it readable while at it.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: konrad.wilk@oracle.com
Fixes: 6e96366933 ("x86, iommu: Update header comments with appropriate naming")
Link: http://lkml.kernel.org/r/1428508017-5316-1-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
It used to be used to check for _TIF_IA32, but the check has
been removed.
Remove GET_THREAD_INFO() too.
Run-tested.
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1428439424-7258-7-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Jumping to the very next instruction is not very useful:
jmp label
label:
Removing the jump.
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1428439424-7258-5-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This is a preparatory patch for moving stub32_execve[at]() to this
file. It makes sense to have all execve stubs in one place, so
that they can reuse code.
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1428439424-7258-2-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
trivial conflict in net/socket.c and non-trivial one in crypto -
that one had evaded aio_complete() removal.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Broadcom BCM63xx DSL SoCs utilize BMIPS CPUs, and as such are required
to perform a read-ahead cache flush after a DMA transfer. Utilize
asm/bmips.h to provide a plat_post_dma_flush_hook, and
mach-generic/dma-coherence.h for everything else.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/9726/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Instead of having platforms to copy the entirety of
mach-generic/dma-coherence.h, check whether these platforms have already
defined a plat_post_dma_flush hook, and if not, provide an inline stub.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/9725/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mach-bmips/dma-coherence.h contains the
plat_post_dma_flush implementation which is not specific to mach-bmips,
but required for all BMIPS-based systems.
Move plat_post_dma_flush to arch/mips/include/asm/bmips.h, rename it to
bmips_post_dma_flush such that other platforms like bcm63xx can utilize
it.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/9724/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The rule for 'copy_from_user()' is that it zeroes the remaining kernel
buffer even when the copy fails halfway, just to make sure that we don't
leave uninitialized kernel memory around. Because even if we check for
errors, some kernel buffers stay around after thge copy (think page
cache).
However, the x86-64 logic for user copies uses a copy_user_generic()
function for all the cases, that set the "zerorest" flag for any fault
on the source buffer. Which meant that it didn't just try to clear the
kernel buffer after a failure in copy_from_user(), it also tried to
clear the destination user buffer for the "copy_in_user()" case.
Not only is that pointless, it also means that the clearing code has to
worry about the tail clearing taking page faults for the user buffer
case. Which is just stupid, since that case shouldn't happen in the
first place.
Get rid of the whole "zerorest" thing entirely, and instead just check
if the destination is in kernel space or not. And then just use
memset() to clear the tail of the kernel buffer if necessary.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
All Marvell EBU SoCs (Kirkwood, Dove, Orion, Armada) have the
capability of changing the location of their internal registers (i.e
the registers for most hardware blocks inside the SoC). When coming
out of reset, the internal registers are mapped at 0xd0000000, but
since years and years, the tradition has been to have the internal
registers remapped at 0xf1000000 by the bootloader, and Linux has
since then assumed that the internal registers for the SoC were
located at 0xf1000000 on Kirkwood, Dove, Orion, etc. Linux has never
been aware that those registers are remappable (and there is no way to
know where they are mapped at runtime, since the register to configure
the address of the registers is itself within the internal registers).
Then came the Armada 370 and Armada XP, in which some of the very
early silicon steppings had an issue, which forced to use 0xd0000000:
the SoC was no longer working properly when the internal registers
were remapped at 0xf1000000. This issue is only affecting very early
silicon steppings and production steppings are not affected: the issue
has been fixed in between.
Since what we (Free Electrons) used to do the initial submission of
the Armada 370 and Armada XP platforms was evaluation boards with
those very early steppings, we submitted Device Tree that assumed the
internal registers were mapped at 0xd0000000. This is the case for
Armada 370 DB, Armada XP DB and Armada XP GP.
However, in practice, since Marvell has been shipping the evaluation
boards with production steppings of the SoC, they are shipping those
boards with bootloaders that remap the registers to 0xf1000000. We
have already changed this internal register address to 0xf1000000 for
the Armada XP DB in commit 82066bdb5a and for the Armada XP GP in
commit 91ed32200e (both merged in v3.15).
We only recently got our hand on an Armada 370 DB with a production
stepping of the SoC, which uses a bootloader that remaps internal
registers at 0xf1000000. Therefore, this commit aligns the Armada 370
DB to be like the Armada XP DB and Armada XP GP: assume that the
internal registers are mapped at 0xf1000000.
We would like to stress out the fact that the usage of 0xd0000000 as
the internal register base address was a temporary workaround for
early steppings deficiencies, and that the real long-term solution is
the usage of 0xf1000000. Having 0xd0000000 is an *accident* in the
life of the Marvell platform support in the kernel, as is confirmed by
the usage of 0xf1000000 in all previous Marvell platforms (Dove,
Kirkwood, Orion).
There are unfortunately a number of commercial devices that continue
to use 0xd0000000 even though they use production steppings of the
SoC, simply because the vendors of such devices have never bothered
using a more recent bootloader version from Marvell. There is not much
we can do about it, and we plan on keeping 0xd0000000 in the Device
Tree of such devices.
The main reason for remapping the internal registers at 0xf1000000
instead of 0xd0000000 is that it leaves more space in the 0 -> 4 GB
part of the physical address space for RAM. With registers at
0xd0000000, all RAM between 0xd0000000 to 0xffffffff is lost because
it's covered by the I/O registers.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Jason Cooper <jason@lakedameon.net>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Dirty logging tracks sptes in 4k granularity, meaning that large sptes
have to be split. If live migration is successful, the guest in the
source machine will be destroyed and large sptes will be created in the
destination. However, the guest continues to run in the source machine
(for example if live migration fails), small sptes will remain around
and cause bad performance.
This patch introduce lazy collapsing of small sptes into large sptes.
The rmap will be scanned in ioctl context when dirty logging is stopped,
dropping those sptes which can be collapsed into a single large-page spte.
Later page faults will create the large-page sptes.
Reviewed-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wanpeng Li <wanpeng.li@linux.intel.com>
Message-Id: <1428046825-6905-1-git-send-email-wanpeng.li@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
CR2 is not cleared as it should after reset. See Intel SDM table named "IA-32
Processor States Following Power-up, Reset, or INIT".
Signed-off-by: Nadav Amit <namit@cs.technion.ac.il>
Message-Id: <1427933438-12782-5-git-send-email-namit@cs.technion.ac.il>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
DR0-DR3 are not cleared as they should during reset and when they are set from
userspace. It appears to be caused by c77fb5fe6f ("KVM: x86: Allow the guest
to run with dirty debug registers").
Force their reload on these situations.
Signed-off-by: Nadav Amit <namit@cs.technion.ac.il>
Message-Id: <1427933438-12782-4-git-send-email-namit@cs.technion.ac.il>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
After reset, the CPU can change the BSP, which will be used upon INIT. Reset
should return the BSP which QEMU asked for, and therefore handled accordingly.
To quote: "If the MP protocol has completed and a BSP is chosen, subsequent
INITs (either to a specific processor or system wide) do not cause the MP
protocol to be repeated."
[Intel SDM 8.4.2: MP Initialization Protocol Requirements and Restrictions]
Signed-off-by: Nadav Amit <namit@cs.technion.ac.il>
Message-Id: <1427933438-12782-3-git-send-email-namit@cs.technion.ac.il>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
recalculate_apic_map() uses two passes over all VCPUs. This is a relic
from time when we selected a global mode in the first pass and set up
the optimized table in the second pass (to have a consistent mode).
Recent changes made mixed mode unoptimized and we can do it in one pass.
Format of logical MDA is a function of the mode, so we encode it in
apic_logical_id() and drop obsoleted variables from the struct.
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Message-Id: <1423766494-26150-5-git-send-email-rkrcmar@redhat.com>
[Add lid_bits temporary in apic_logical_id. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
We want to support mixed modes and the easiest solution is to avoid
optimizing those weird and unlikely scenarios.
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Message-Id: <1423766494-26150-4-git-send-email-rkrcmar@redhat.com>
[Add comment above KVM_APIC_MODE_* defines. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Broadcast allowed only one global APIC mode, but mixed modes are
theoretically possible. x2APIC IPI doesn't mean 0xff as broadcast,
the rest does.
x2APIC broadcasts are accepted by xAPIC. If we take SDM to be logical,
even addreses beginning with 0xff should be accepted, but real hardware
disagrees. This patch aims for simple code by considering most of real
behavior as undefined.
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Message-Id: <1423766494-26150-3-git-send-email-rkrcmar@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
In mixed modes, we musn't deliver xAPIC IPIs like x2APIC and vice versa.
Instead of preserving the information in apic_send_ipi(), we regain it
by converting all destinations into correct MDA in the slow path.
This allows easier reasoning about subsequent matching.
Our kvm_apic_broadcast() had an interesting design decision: it didn't
consider IOxAPIC 0xff as broadcast in x2APIC mode ...
everything worked because IOxAPIC can't set that in physical mode and
logical mode considered it as a message for first 8 VCPUs.
This patch interprets IOxAPIC 0xff as x2APIC broadcast.
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Message-Id: <1423766494-26150-2-git-send-email-rkrcmar@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Drop unused static procedure which doesn't have callers within its
translation unit. It had been already removed independently in QEMU[1]
from the OpenPIC implementation borrowed from the kernel.
[1] https://lists.gnu.org/archive/html/qemu-devel/2014-06/msg01812.html
Signed-off-by: Arseny Solokha <asolokha@kb.kras.ru>
Cc: Alexander Graf <agraf@suse.de>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <1424768706-23150-3-git-send-email-asolokha@kb.kras.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
After speed-up of cpuid_maxphyaddr() it can be called frequently:
instead of heavyweight enumeration of CPUID entries it returns a cached
pre-computed value. It is also inlined now. So caching its result became
unnecessary and can be removed.
Signed-off-by: Eugene Korenevsky <ekorenevsky@gmail.com>
Message-Id: <20150329205644.GA1258@gnote>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
On each VM-entry CPU should check the following VMCS fields for zero bits
beyond physical address width:
- APIC-access address
- virtual-APIC address
- posted-interrupt descriptor address
This patch adds these checks required by Intel SDM.
Signed-off-by: Eugene Korenevsky <ekorenevsky@gmail.com>
Message-Id: <20150329205627.GA1244@gnote>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
cpuid_maxphyaddr(), which performs lot of memory accesses is called
extensively across KVM, especially in nVMX code.
This patch adds a cached value of maxphyaddr to vcpu.arch to reduce the
pressure onto CPU cache and simplify the code of cpuid_maxphyaddr()
callers. The cached value is initialized in kvm_arch_vcpu_init() and
reloaded every time CPUID is updated by usermode. It is obvious that
these reloads occur infrequently.
Signed-off-by: Eugene Korenevsky <ekorenevsky@gmail.com>
Message-Id: <20150329205612.GA1223@gnote>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Exposing the on-stack error code with internal error is cheap and
potentially useful.
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Message-Id: <1428001865-32280-1-git-send-email-rkrcmar@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
If we were migrated right after __getcpu, but before reading the
migration_count, we wouldn't notice that we read TSC of a different
VCPU, nor that KVM's bug made pvti invalid, as only migration_count
on source VCPU is increased.
Change vdso instead of updating migration_count on destination.
Cc: stable@vger.kernel.org
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Fixes: 0a4e6be9ca ("x86: kvm: Revert "remove sched notifier for cross-cpu migrations"")
Message-Id: <1428000263-11892-1-git-send-email-rkrcmar@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The newly-added tracepoint shows the following results on
the tscdeadline_latency test:
qemu-kvm-8387 [002] 6425.558974: kvm_vcpu_wakeup: poll time 10407 ns
qemu-kvm-8387 [002] 6425.558984: kvm_vcpu_wakeup: poll time 0 ns
qemu-kvm-8387 [002] 6425.561242: kvm_vcpu_wakeup: poll time 10477 ns
qemu-kvm-8387 [002] 6425.561251: kvm_vcpu_wakeup: poll time 0 ns
and so on. This is because we need to go through kvm_vcpu_block again
after the timer IRQ is injected. Avoid it by polling once before
entering kvm_vcpu_block.
On my machine (Xeon E5 Sandy Bridge) this removes about 500 cycles (7%)
from the latency of the TSC deadline timer.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Rename the old __vcpu_run to vcpu_run, and extract part of it to a new
function vcpu_block.
The next patch will add a new condition in vcpu_block, avoid extra
indentation.
Reviewed-by: David Matlack <dmatlack@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Guest can't be booted w/ ept=0, there is a message dumped as below:
If you're running a guest on an Intel machine without unrestricted mode
support, the failure can be most likely due to the guest entering an invalid
state for Intel VT. For example, the guest maybe running in big real mode
which is not supported on less recent Intel processors.
EAX=00000011 EBX=f000d2f6 ECX=00006cac EDX=000f8956
ESI=bffbdf62 EDI=00000000 EBP=00006c68 ESP=00006c68
EIP=0000d187 EFL=00000004 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =e000 000e0000 ffffffff 00809300 DPL=0 DS16 [-WA]
CS =f000 000f0000 ffffffff 00809b00 DPL=0 CS16 [-RA]
SS =0000 00000000 ffffffff 00809300 DPL=0 DS16 [-WA]
DS =0000 00000000 ffffffff 00809300 DPL=0 DS16 [-WA]
FS =0000 00000000 ffffffff 00809300 DPL=0 DS16 [-WA]
GS =0000 00000000 ffffffff 00809300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 000f6a80 00000037
IDT= 000f6abe 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000
DR6=00000000ffff0ff0 DR7=0000000000000400
EFER=0000000000000000
Code=01 1e b8 6a 2e 0f 01 16 74 6a 0f 20 c0 66 83 c8 01 0f 22 c0 <66> ea 8f d1 0f 00 08 00 b8 10 00 00 00 8e d8 8e c0 8e d0 8e e0 8e e8 89 c8 ff e2 89 c1 b8X
X86 eflags bit 1 is fixed set, which means that 1 << 1 is set instead of 1,
this patch fix it.
Signed-off-by: Wanpeng Li <wanpeng.li@linux.intel.com>
Message-Id: <1428473294-6633-1-git-send-email-wanpeng.li@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Interrupt entry points are handled with the following code,
each 32-byte code block contains seven entry points:
...
[push][jump 22] // 4 bytes
[push][jump 18] // 4 bytes
[push][jump 14] // 4 bytes
[push][jump 10] // 4 bytes
[push][jump 6] // 4 bytes
[push][jump 2] // 4 bytes
[push][jump common_interrupt][padding] // 8 bytes
[push][jump]
[push][jump]
[push][jump]
[push][jump]
[push][jump]
[push][jump]
[push][jump common_interrupt][padding]
[padding_2]
common_interrupt:
And there is a table which holds pointers to every entry point,
IOW: to every push.
In cold cache, two jumps are still costlier than one, even
though we get the benefit of them residing in the same
cacheline.
This change replaces short jumps with near ones to
'common_interrupt', and pads every push+jump pair to 8 bytes. This
way, each interrupt takes only one jump.
This change replaces ".p2align CONFIG_X86_L1_CACHE_SHIFT" before
dispatch table with ".align 8" - we do not need anything
stronger than that.
The table of entry addresses (the interrupt[] array) is no
longer necessary, the address of entries can be easily
calculated as (irq_entries_start + i*8).
text data bss dec hex filename
12546 0 0 12546 3102 entry_64.o.before
11626 0 0 11626 2d6a entry_64.o
The size decrease is because 1656 bytes of .init.rodata are
gone. That's initdata, though. The resident size does go up a
bit.
Run-tested (32 and 64 bits).
Acked-and-Tested-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1428090553-7283-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This change does two things:
Copy-pastes "retint_swapgs:" code into syscall handling code,
the copy is under "syscall_return:" label. The code is unchanged
apart from some label renames.
Removes "opportunistic sysret" code from "retint_swapgs:" code
block, since now it won't be reached by syscall return. This in
fact removes most of the code in question.
text data bss dec hex filename
12530 0 0 12530 30f2 entry_64.o.before
12562 0 0 12562 3112 entry_64.o
Run-tested.
Acked-and-Tested-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1427993219-7291-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Following the arrangement for processors that wire FPU exceptions to the
FPE CPU exception handle the case where no FPU is in use -- which for
DECstation systems will only ever happen when the "nofpu" kernel option
has been used -- do not register the FPU interrupt in such a case
either.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9714/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Implement a cheap way to count FPU interrupts for R2k/R3k DECstation
systems. Do this manually in handcoded assembly, rather than calling
`kstat_incr_irq_this_cpu' that would require setting up a stack frame
and a lot of redirection. This is not going to be a problem because the
FPU interrupt is local to the CPU and also there is one CPU only anyway.
So at bootstrap determine the address of the correct location within
`struct irq_desc', and then only refer to it directly in the interrupt
handler.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9713/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Factor out FPU feature probing, mainly to remove code duplication from
`fpu_disable'. No functional change although shuffle some code to avoid
forward references.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9712/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Define the central place the default FCSR value is set from, initialised
in `cpu_probe'. Determine the FCSR mask applied to values written to
the register with CTC1 in the full emulation mode and via ptrace(2),
according to the ISA level of processor hardware or the writability of
bits 31:18 if actual FPU hardware is used.
Software may rely on FCSR bits whose functions our emulator does not
implement, so it should not allow them to be set or software may get
confused. For ptrace(2) it's just sanity.
[ralf@linux-mips.org: Fixed double inclusion of <asm/current.h>.]
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9711/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The ABS.fmt and NEG.fmt instructions have been specified as arithmetic
in the MIPS architecture, which in particular implies handling NaN data
in the usual way with qNaN bit patterns propagated unchanged and sNaN
bit patterns signalling the usual IEEE 754 Invalid Operation exception
and quieted by default.
A series of changes applied over time to our implementation:
c5033d78 [MIPS] ieee754[sd]p_neg workaround
cea2be44 MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
has led to the current situation where the sign bit is updated according
to the operation requested even for NaN inputs. This is according to
these commits a workaround so that broken binaries produced by GCC
disregarding the properties of these instructions have a chance to work.
For sNaN inputs this remains within IEEE Std 754 as the standard leaves
the choice of output qNaN bit patterns produced under the default
Invalid Operation exception handling for individual sNaN input bit
patterns to implementer's discretion, even though it still recommends as
much NaN input information to be preserved in NaN outputs.
For qNaN inputs however it violates the standard as it requires a qNaN
input bit patterns to propagate unchanged to output.
This is also unlike real MIPS FPU hardware behaves where sNaN and/or
qNaN processing has been fully implemented with no Unimplemented
Operation exception signalled. Such hardware propagates any input qNaN
bit pattern unchanged. It also quiets any input sNaN bit pattern in an
implementer-specific manner, for example the MIPS 74Kf processor returns
the default qNaN pattern with the sign bit always clear and the Broadcom
SB-1 and BMIPS5000 processors propagate the input sNaN bit pattern with
the sign bit unchanged and the quiet bit first cleared in the trailing
significand field and then the next lower bit set if clearing the quiet
bit left the field with no other bit set.
Especially the latter observation indicates the limited usefulness of
the workaround as it will cover many hardware configurations, but not
all of them, only making it harder to discover such broken binaries that
need to be recompiled with GCC told to avoid the use of ABS.fmt and
NEG.fmt instructions where non-arithmetic semantics is required by the
algorithm used.
Revert the damage done by the series of changes then, and take the
opportunity to simplify implementation by calling `ieee754dp_sub' and
`ieee754dp_add' as required and also the rounding mode set towards -Inf
temporarily so that the sign of 0 is correctly handled.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9710/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Define IEEE 754-2008 feature control bits: FIR.HAS2008, FCSR.ABS2008 and
FCSR.NAN2008, and update the `_ieee754_csr' structure accordingly.
For completeness define FIR.UFRP too.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Implement the FCCR, FEXR and FENR "shadow" FPU registers for the
architecture levels that include them, for the CFC1 and CTC1
instructions in the full emulation mode.
For completeness add macros for the CP1 UFR and UNFR registers too, no
actual implementation though.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9708/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Implement FIR feature flags in the FPU emulator according to features
supported and architecture level requirements. The W, L and F64 bits
have only been added at level #2 even though the features they refer to
were also included with the MIPS64r1 ISA and the W fixed-point format
also with the MIPS32r1 ISA.
This is only relevant for the full emulation mode and the emulated CFC1
instruction as well as ptrace(2) accesses.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9707/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Correct an ISA level determination problem introduced with 8b8aa636
[MIPS: kernel: cpu-probe.c: Add support for MIPS R6], reverting explicit
masking against individual `MIPS_CPU_ISA_*' macros in FPU feature
determination.
Feature macros such as `cpu_has_mips_r' cannot be used here, because
they operate on CPU #0 and we want to refer to the current CPU instead.
They cannot be used for masking against the current CPU either because
they mask against CPU #0 too, e.g.:
# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9706/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Rework `process_fpemu_return' and move IEEE 754 exception interpretation
there, from `do_fpe'. Record the cause bits set in FCSR before they are
cleared and pass them through to `process_fpemu_return' so as to set
`si_code' correctly too for SIGFPE signals sent from emulation rather
than those issued by hardware with the FPE processor exception only.
For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised
and only sets it to anything if an FPU instruction has been emulated,
which in turn is the only case SIGFPE can be issued for here.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9705/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Clear any FCSR cause bits recorded in the saved FPU context after
emulation in all cases rather than in `do_fpe' only, so that any
unmasked IEEE 754 exception left from emulation does not cause a fatal
kernel-mode FPE hardware exception with the CTC1 instruction used by the
kernel to subsequently restore FCSR hardware from the saved FPU context.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9704/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Respect the FCSR exception mask when interpreting the IEEE 754 exception
condition to report with SIGFPE in `si_code', so as not to use one that
has been masked where a different one set in parallel caused the FPE
hardware exception to trigger. As per the IEEE Std 754 the Inexact
exception can happen together with Overflow or Underflow.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9703/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Complement 593d33fe [MIPS: math-emu: Move various objects into an ar
library.] and also move sp_tlong.o, sp_flong.o, dp_tlong.o, and
dp_flong.o into an `ar' library. These objects implement long
fixed-point format support that can be omitted from MIPS I, MIPS II and
MIPS32r1 configurations.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9702/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Restore EPC at the branch whose delay slot is emulated if the delay-slot
instruction signals. This is so that code in `fpu_emulator_cop1Handler'
does not see EPC having advanced and mistakenly successfully resume
userland execution from the location at the branch target in that case.
Restoring EPC guarantees an immediate exit from the emulation loop and
if EPC hasn't advanced at all since entering the loop, also issuing the
signal reported by the delay-slot instruction.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9701/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Correct ISA requirements for floating-point instructions:
* the CU3 exception signifies a real COP3 instruction in MIPS I & II,
* the BC1FL and BC1TL instructions are not supported in MIPS I,
* the SQRT.fmt instructions are indeed supported in MIPS II,
* the LDC1 and SDC1 instructions are indeed supported in MIPS32r1,
* the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions
are indeed supported in MIPS32,
* the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in
MIPS32r2 and MIPS32r6,
* the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions
are indeed supported in MIPS32r2 and MIPS32r6,
* the RSQRT.fmt and RECIP.fmt instructions are indeed supported in
MIPS64r1,
Also simplify conditionals for MIPS III and MIPS IV FPU instructions and
the handling of the MOVCI minor opcode.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9700/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Implement the correct ordering of individual floating-point registers
within double-precision register pairs for the MIPS I FP context, as
required by our FP emulation code and expected by userland talking via
ptrace(2). Use L.D and S.D assembly macros that do the right thing like
LDC1 and SDC1 from MIPS II up, avoiding the need to mess up with
endianness conditionals.
This in particular fixes the handling of denormals and NaN generation in
Unimplemented Operation emulation traps.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9699/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Correct a cache coherency regression introduced with be1664c4 [Another
round of fixes for the fp emulator.] for the emulation frame used in
delay-slot emulation.
Two instructions are copied into the frame and as from the commit
referred a cache synchronisation call is made for the second instruction
aka `badinst' of the two only. The `flush_cache_sigtramp' interface is
reused that guarantees that synchronisation will be made for 8 bytes or
2 instructions starting from the address requested, although if cache
lines are wider then a larger area may be synchronised.
Change the call to point to the first of the two instructions aka `emul'
instead, removing unpredictable behaviour resulting from cache
incoherency.
This bug only ever manifested itself on systems implementing 4-byte
cache lines, typically MIPS I systems, causing all kinds of weirdness.
This is because the sequence of two instructions starting from `emul' is
8-byte aligned and for 8-byte or wider cache lines the line synchronised
will span both, so the vast majority of systems have escaped unharmed.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9698/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Do not lose the other half of the BREAK code where there is an upper
half. This is so that e.g. `BREAK 7, 7' is not interpreted as a divide
by zero trap, while `BREAK 0, 7' or `BREAK 7, 0' still are.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9697/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add the missing microMIPS BREAK16 instruction code interpretation and
reshape code removing instruction fetching duplication and the separate
call to `do_trap_or_bp' in the MIPS16 path.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9696/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Correct the interpretation of the immediate MIPS16 BREAK instruction
code embedded in the instruction word across bits 10:5 rather than 11:6
as current code implies, fixing the interpretation of integer overflow
and divide by zero traps.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9695/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The `cpu_has_fpu' feature flag must not be hardcoded to 1 or the `nofpu'
kernel option will be ignored. Remove any such overrides and add a
cautionary note. Hardcoding to 0 is fine for FPU-less platforms.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9694/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The `ieee754sp_isnan' and `ieee754dp_isnan' NaN classifiers are now no
longer externally referred, remove their header prototypes and make them
local to the two only respective places still making use of them.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9693/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Rewrite qNaN handling in `ieee754sp_fdp' using the `ieee754_class_nan'
helper recently added, removing the external call to `ieee754sp_isnan'
and reducing the size of code by 16 instructions or 64 bytes.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9692/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Remove a redundant call to `ieee754_setandtestcx' in `ieee754sp_cmp' and
`ieee754dp_cmp'. The IEEE 754 exception requested will have already
been set by a call to `ieee754_setcx' immediately above, because `sig'
has to be non-zero to reach here, and the comparison result returned
will be 0 regardless of the result from the call. Simplify the return
expression remaining. All this reducing the size of code by 16 and 12
instructions or 64 and 48 bytes respectively.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9690/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We have the input operands already classified in `ieee754sp_cmp' and
`ieee754dp_cmp' comparison operations, so use the class obtained to tell
NaNs and numbers apart rather than classifying inputs again for this
purpose, reducing the size of code by 24 and 40 instructions or 96 and
160 bytes respectively.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9689/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Revert the changes made by commit fdffbafb [Lots of FPU bug fixes from
Kjeld Borch Egevang.] to `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt'
sNaN quieting handlers and their callers so that sNaN processing is done
within the handlers againg. Pass the sNaN causing an IEEE 754 invalid
operation exception down to the relevant handler. Pass the sNaN in `fs'
where two sNaNs are supplied to a binary operation.
Set the Invalid Operation FCSR exception bits in the quieting handlers
rather than at their call sites throughout. Make the handlers exclusive
for sNaN processing.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9688/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Don't call the `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' sNaN quieting
handlers for a qNaN supplied to floating-point format conversions or
SQRT.S/SQRT.D instructions, or for a qNaN produced out of a negative
operand supplied to SQRT.S/SQRT.D instructions. Return the qNaN right
away in these cases.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9687/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.]
replaced the two single `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt'
places, where sNaN quieting used to happen for single and double
floating-point operations respectively, with individual qNaN
instantiations across all the call sites instead. It also made most of
these two functions dead code as where called on a qNaN they return
right away.
To revert the damage and make sNaN quieting uniform again first rewrite
`ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' to do the same quieting all
the call sites do, that is return the default qNaN encoding for all
input sNaN values; never propagate any sNaN payload bits from its
trailing significand field.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9685/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Replace a hardcoded numeric bitmask for FCSR cause bits with
`FPU_CSR_ALL_X' in `__build_clear_fpe'.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9684/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Changes applied to `do_cpu' over time reduced the use of the SIGILL
issued with `force_sig' at the end to a single CU3 case only in the
switch statement there. Move that `force_sig' call over to right where
required then and toss out the pile of gotos now not needed to skip over
the call, replacing them with regular breaks out of the switch.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9683/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Move CFC1/CTC1 emulation code to separate functions to avoid excessive
indentation in forthcoming changes. Adjust formatting in a minor way
and remove extraneous round brackets.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9682/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
GCC is smart enough to substitute the final result for FLS calculations
as implemented in the fallback C code we have in `__fls' and `fls'
applied to constant values. The presence of inline asm defeats the
compiler though, forcing it to emit extraneous CLZ/DCLZ calculation for
processors that support these instructions.
Use `__builtin_constant_p' then to avoid inline asm altogether for
constants.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9681/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit 56a64733 [MIPS: math-emu: Switch to using the MIPS rounding
modes.] removed the distinction between hardware and emulator rounding
mode encodings, the hardware encoding is now used in emulation as well.
Complement the change and remove the `modeindex' macro previously used
for indexing into encoding translation tables, it now does nothing and
only obfuscates code by reinserting the value extracted from FCSR.
Adjust comments accordingly.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9680/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fold a nested `if' statement for the R6 case in `do_ri' into its
containing `if' block, removing excessive indentation causing code to
extend beyond 79 columns.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9679/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Use `static inline' rather than `static __maybe_unused' for
`mipsr2_decoder' in the empty case, making inlining explicit where it
will happen anyway.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9678/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit 46490b57 [MIPS: kernel: elf: Improve the overall ABI and FPU mode
checks] reduced `get_fp_abi' to an elaborate pass-through. Drop it
then.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9677/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Correct a copy-and-paste issue with the description for `movf_func'
referring to `movt_func'. Reformat the former function to match the
latter.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9675/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reword the comment for `__cpu_has_fpu' to make it unambiguous this code
is for external floating-point units only, generally MIPS I processors
using the original CP1 hardware interface.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9673/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Adjust the explanatory comment for FPU emulator traps according to
ba3049ed [MIPS: Switch FPU emulator trap to BREAK instruction.];
originally coming from `do_ade'.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9672/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add the remaining missing comments for IEEE 754 special value array
indices. Reindent macro definitions for consistency.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9671/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
IEEE754_SPCVAL_NMIN denotes the index into the special value array where
the closest to zero negative normal number expressible is stored.
Similarly IEEE754_SPCVAL_NMIND denotes such index for the closest to
zero negative subnormal number expressible. Make comments match that.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9670/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reindent CP0 Cause macros for a single space after #define, leaving
extra indentation for individual Interrupt Pending bits as with CP0
Status register's Interrupt Mask bits.
[ralf@linux-mips.org: Fix conflict.]
[ralf@linux-mips.org: Fix indentation of the CAUSEB_FDCI and CAUSEF_FDCI
definitions.]
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9669/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
TX39 CP0 Configuration Register 3 macro definitions have been randomly
thrown in the middle of a block of CP0 Status register value macros.
Move them to the end of the whole CP0 register value macro block,
complementing the location of the TX39 Cache register name macro at the
end of the CP0 register name macro block.
[ralf@linux-mips.org: Fix conflict.]
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9668/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Originally CP1 macros were placed between CP0 register name macros and
CP0 register value macros. As changes were applied to the header the
position of CP1 macros gradually has become more and more arbitrary and
two separate blocks were created. This may only cause confusion.
Move them out of the way then and place together after all the CP0
macros. No semantic change.
[ralf@linux-mips.org: Fix conflict.]
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9667/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Remove a duplicate FPU Status Register reference that has been there
since forever and a mistakenly copied and pasted R4xx0 manual reference.
[ralf@linux-mips.org: Fix conflict.]
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9666/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
New code will require TRACE_SYSTEM to be a valid C variable name,
but some tracepoints have TRACE_SYSTEM with '-' and not '_', so
it can not be used. Instead, add a TRACE_SYSTEM_VAR that can
give the tracing infrastructure a unique name for the trace system.
Link: http://lkml.kernel.org/r/20150402111500.5e52c1ed.cornelia.huck@de.ibm.com
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: David Hildenbrand <dahi@linux.vnet.ibm.com>
Cc: Christian Borntraeger <borntraeger@de.ibm.com>
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Reviewed-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Tested-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
1. Assorted changes
1.1 allow more feature bits for the guest
1.2 Store breaking event address on program interrupts
2. Interrupt handling rework
2.1 Fix copy_to_user while holding a spinlock (cc stable)
2.2 Rework floating interrupts to follow the priorities
2.3 Allow to inject all local interrupts via new ioctl
2.4 allow to get/set the full local irq state, e.g. for migration
and introspection
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.14 (GNU/Linux)
iQIcBAABAgAGBQJVGvEUAAoJEBF7vIC1phx82tEP/3KrwsDRs+buiBqyv9k+qCFV
v+R94gReBB5ggfbGfUYgBJMR2/4XQ+0jcZ55jfBCC4osOq6Juw/8HIj2nSgbQHmz
F9Go0n8IqJ3DnqPTc0KYdFZ7kqDvMV5ME3XJrFiAHv1TUL9H/KpZArkcVIwD2NOo
w01AVrCDY4bTajYqKShzGFymQl1K5vTGGvgxhh4kAHct4Nt5N5HFmyROm0RrsFZx
Sycx4t177O7zhCN2tv5Zy8iWaEvzHAESoXkhZ2cJ6t+FXii2Eov5IgyyfYRXBfbm
YACyvlFD087UdFGTt85ggPVS/S/5hn9xXmVHuIimHeyZU7CXCN5vYPcn+ZyksYr5
uA8+/2OPAgcaeDa2f7nCjl8jmcLR3hkQ0n/urA+pPYAZANJoFDfiGOr/kVk6aKff
JTGSFUjNK891/IGEsdrSk2p64U5xMd8LFa3Il++kZT91gc2nrZOHNz5FGlXlkLdJ
sADeNFWhoprEt/2P4aX6W2j26L8G874XkldDSjrS41U8L55+IiEm09r8oAWgfc5A
pryeDaN4nSjFC+HOtlPkcVkAcsswiI6nHIm3+/XFetCq+v4pnVKFMHWsTeEjiQgQ
H5aV9mfEKTJaCPrAJMsj8ZsKq0usG+BeRNqpIvxPAQB8fyl3jw9iu+RHeY1xWsTg
BRHB/+CGYIxDu4XdRexv
=Rrx5
-----END PGP SIGNATURE-----
Merge tag 'kvm-s390-next-20150331' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD
Features and fixes for 4.1 (kvm/next)
1. Assorted changes
1.1 allow more feature bits for the guest
1.2 Store breaking event address on program interrupts
2. Interrupt handling rework
2.1 Fix copy_to_user while holding a spinlock (cc stable)
2.2 Rework floating interrupts to follow the priorities
2.3 Allow to inject all local interrupts via new ioctl
2.4 allow to get/set the full local irq state, e.g. for migration
and introspection
Fixes page refcounting issues in our Stage-2 page table management code,
fixes a missing unlock in a gicv3 error path, and fixes a race that can
cause lost interrupts if signals are pending just prior to entering the
guest.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJVBs95AAoJEEtpOizt6ddyAfoH/Rwj2T38ZDikImPpgfeFrmJs
ZlWC+Z3akwjVHPv308/MsKdyashtA7OjiMp3DOheMFMYJay/ecgY/92vFCc6uh5S
LDoXCbp+Pneth6C6bbU2Gw+aoCD07ZYCn9PeFq40MfpQUhCEGWhx41OFzHppqOZx
e+jodHRE+sBVTFUtbz+HubAfcM46f/8bP7682CEKsVZPeTSiHyeojdZEglfB37MG
ar/iC1/cyO/097vWaBqv1t1WZoHbWmMrDlzo5X+AtayVXFNdv4Ztw0Rz2kRhnLB8
8GXYawoSQoTN8FX1oyTyr5YWcWD7wDTzhcHsHS1xZHhvrdLCEcFrHeEWkuUlYjU=
=YS6j
-----END PGP SIGNATURE-----
Merge tag 'kvm-arm-fixes-4.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into 'kvm-next'
Fixes for KVM/ARM for 4.0-rc5.
Fixes page refcounting issues in our Stage-2 page table management code,
fixes a missing unlock in a gicv3 error path, and fixes a race that can
cause lost interrupts if signals are pending just prior to entering the
guest.
The Cortex A9 tile fails to unplug CPUs if errata 643719 is not enabled.
This leads to random weird behaviours, but ultimately seem to lock the
kernel one way or another when a CPU is hot unplugged.
Symptoms range from a spinlock lockup in the scheduler, the entire
system hanging, to dumping out the kernel printk buffer a few lines at
a time, and other weird behaviours.
This is caused by the outgoing CPU not having its inner caches properly
flushed before it exits coherency - flush_cache_louis() is used to
achieve this, but as a result of the hardware bug, this function ends
up doing nothing without the errata workaround enabled.
As the Versatile Express has an affected CPU, this errata must always
be enabled.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
I got below kernel panic during kdump test on Thinkpad T420
laptop:
[ 0.000000] No NUMA configuration found
[ 0.000000] Faking a node at [mem 0x0000000000000000-0x0000000037ba4fff]
[ 0.000000] Kernel panic - not syncing: stack-protector: Kernel stack is corrupted in: ffffffff81d21910
...
[ 0.000000] Call Trace:
[ 0.000000] [<ffffffff817c2a26>] dump_stack+0x45/0x57
[ 0.000000] [<ffffffff817bc8d2>] panic+0xd0/0x204
[ 0.000000] [<ffffffff81d21910>] ? numa_clear_kernel_node_hotplug+0xe6/0xf2
[ 0.000000] [<ffffffff8107741b>] __stack_chk_fail+0x1b/0x20
[ 0.000000] [<ffffffff81d21910>] numa_clear_kernel_node_hotplug+0xe6/0xf2
[ 0.000000] [<ffffffff81d21e5d>] numa_init+0x1a5/0x520
[ 0.000000] [<ffffffff81d222b1>] x86_numa_init+0x19/0x3d
[ 0.000000] [<ffffffff81d22460>] initmem_init+0x9/0xb
[ 0.000000] [<ffffffff81d0d00c>] setup_arch+0x94f/0xc82
[ 0.000000] [<ffffffff81d05120>] ? early_idt_handlers+0x120/0x120
[ 0.000000] [<ffffffff817bd0bb>] ? printk+0x55/0x6b
[ 0.000000] [<ffffffff81d05120>] ? early_idt_handlers+0x120/0x120
[ 0.000000] [<ffffffff81d05d9b>] start_kernel+0xe8/0x4d6
[ 0.000000] [<ffffffff81d05120>] ? early_idt_handlers+0x120/0x120
[ 0.000000] [<ffffffff81d05120>] ? early_idt_handlers+0x120/0x120
[ 0.000000] [<ffffffff81d055ee>] x86_64_start_reservations+0x2a/0x2c
[ 0.000000] [<ffffffff81d05751>] x86_64_start_kernel+0x161/0x184
[ 0.000000] ---[ end Kernel panic - not syncing: stack-protector: Kernel sta
This is caused by writing over the end of numa mask bitmap
in numa_clear_kernel_node().
numa_clear_kernel_node() tries to set the node id in a mask bitmap,
by iterating all reserved regions and assuming that every region
has a valid nid.
This assumption is not true because there's an exception for some
graphic memory quirks. See trim_snb_memory() in arch/x86/kernel/setup.c
It is easily to reproduce the bug in the kdump kernel because kdump
kernel use pre-reserved memory instead of the whole memory, but
kexec pass other reserved memory ranges to 2nd kernel as well.
like below in my test:
kdump kernel ram 0x2d000000 - 0x37bfffff
One of the reserved regions: 0x40000000 - 0x40100000 which
includes 0x40004000, a page excluded in trim_snb_memory(). For
this memblock reserved region the nid is not set, it is still
default value MAX_NUMNODES. later node_set will set bit
MAX_NUMNODES thus stack corruption happen.
This also happens when booting with mem= kernel commandline
during my test.
Fixing it by adding a check, do not call node_set in case nid is
MAX_NUMNODES.
Signed-off-by: Dave Young <dyoung@redhat.com>
Reviewed-by: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: bhe@redhat.com
Cc: qiuxishi@huawei.com
Link: http://lkml.kernel.org/r/20150407134132.GA23522@dhcp-16-198.nay.redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This cleanup is prepare to move the driver to drivers/gpio. Custom
definitions of gpio_get_value()/gpio_set_value() are dropped.
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The callers of setbat() are actually passing a pgprot_t for the flags
parameter. This doesn't matter unless STRICT_MM_TYPECHECKS is enabled.
So we can turn that on without breaking the build, change setbat() to
take a pgprot_t and have it convert it to an unsigned long internally.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
The celleb code has seen no actual development for ~7 years.
We (maintainers) have no access to test hardware, and it is highly
likely the code has bit-rotted.
As far as we're aware the hardware was never widely available, and is
certainly no longer available, and no one on the list has shown any
interest in it over the years.
So remove it. If anyone has one and cares please speak up.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Jeremy Kerr <jk@ozlabs.org>
The powernv code has some conditional support for running on bare metal
machines that have no OPAL firmware, but provide RTAS.
No released machines ever supported that, and even in the lab it was
just a transitional hack in the days when OPAL was still being
developed.
So remove the code.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Freescale updates from Scott:
"Highlights include BMan device tree nodes, an MSI erratum workaround, a
couple minor performance improvements, config updates, and misc
fixes/cleanup."
Conflicts:
drivers/net/ethernet/mellanox/mlx4/cmd.c
net/core/fib_rules.c
net/ipv4/fib_frontend.c
The fib_rules.c and fib_frontend.c conflicts were locking adjustments
in 'net' overlapping addition and removal of code in 'net-next'.
The mlx4 conflict was a bug fix in 'net' happening in the same
place a constant was being replaced with a more suitable macro.
Signed-off-by: David S. Miller <davem@davemloft.net>
Take a look at the first instruction byte before optimizing the NOP -
there might be something else there already, like the ALTERNATIVE_2()
in rdtsc_barrier() which NOPs out on AMD even though we just
patched in an MFENCE.
This happens because the alternatives sees X86_FEATURE_MFENCE_RDTSC,
AMD CPUs set it, we patch in the MFENCE and right afterwards it sees
X86_FEATURE_LFENCE_RDTSC which AMD CPUs don't set and we blindly
optimize the NOP.
Checking whether at least the first byte is 0x90 prevents that.
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1428181662-18020-1-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
On failure, sys_execve() does not clobber EXTRA_REGS, so we can
just return to userpsace without saving/restoring them.
On success, ELF_PLAT_INIT() in sys_execve() clears all these
registers.
On other executable formats:
- binfmt_flat.c has similar FLAT_PLAT_INIT, but x86 (and everyone
else except sh) doesn't define it.
- binfmt_elf_fdpic.c has ELF_FDPIC_PLAT_INIT, but x86 (and most
others) doesn't define it.
- There are no such hooks in binfmt_aout.c et al. We inherit
EXTRA_REGS from the prior executable.
This inconsistency was not intended.
This change removes SAVE/RESTORE_EXTRA_REGS in stub_execve,
removes register clearing in ELF_PLAT_INIT(),
and instead simply clears them on success in stub_execve.
Run-tested.
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1428173719-7637-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
The 'pax' argument is unnecesary. Instead, store the RAX value
directly in regs.
This pattern goes all the way back to 2.1.106pre1, when restore_sigcontext()
was changed to return an error code instead of EAX directly:
https://git.kernel.org/cgit/linux/kernel/git/history/history.git/diff/arch/i386/kernel/signal.c?id=9a8f8b7ca3f319bd668298d447bdf32730e51174
In 2007 sigaltstack syscall support was added, where the return
value of restore_sigcontext() was changed to carry the memory-copying
failure code.
But instead of putting 'ax' into regs->ax directly, it was carried
in via a pointer and then returned, where the generic syscall return
code copied it to regs->ax.
So there was never any deeper reason for this suboptimal pattern, it
was simply never noticed after being introduced.
Signed-off-by: Brian Gerst <brgerst@gmail.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1428152303-17154-1-git-send-email-brgerst@gmail.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
the AT91_MEMCTRL_* defines are only used by the pm code, move them to pm.h
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The standby functions are now only used in pm.c, move them there.
Also, they are not inlined as a pointer to those functions is passed to the
cpuidle driver.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
When compiling for multiplatform for both ARMv6 and ARMv7, the default compiler
flags are for ARMv6, and results in:
arch/arm/mach-at91/pm_suspend.S:144: Error: selected processor does not support ARM mode `dsb'
Enforce ARMv7 flags for pm_suspend.o when CPU_V7 is selected.
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Quentin caught a corner case with the generation of instruction
padding in the ALTERNATIVE_2 macro: if len(orig_insn) <
len(alt1) < len(alt2), then not enough padding gets added and
that is not good(tm) as we could overwrite the beginning of the
next instruction.
Luckily, at the time of this writing, we don't have
ALTERNATIVE_2() invocations which have that problem and even if
we did, a simple fix would be to prepend the instructions with
enough prefixes so that that corner case doesn't happen.
However, best it would be if we fixed it properly. See below for
a simple, abstracted example of what we're doing.
So what we ended up doing is, we compute the
max(len(alt1), len(alt2)) - len(orig_insn)
and feed that value to the .skip gas directive. The max() cannot
have conditionals due to gas limitations, thus the fancy integer
math.
With this patch, all ALTERNATIVE_2 sites get padded correctly;
generating obscure test cases pass too:
#define alt_max_short(a, b) ((a) ^ (((a) ^ (b)) & -(-((a) < (b)))))
#define gen_skip(orig, alt1, alt2, marker) \
.skip -((alt_max_short(alt1, alt2) - (orig)) > 0) * \
(alt_max_short(alt1, alt2) - (orig)),marker
.pushsection .text, "ax"
.globl main
main:
gen_skip(1, 2, 4, 0x09)
gen_skip(4, 1, 2, 0x10)
...
.popsection
Thanks to Quentin for catching it and double-checking the fix!
Reported-by: Quentin Casasnovas <quentin.casasnovas@oracle.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20150404133443.GE21152@pd.tnic
Signed-off-by: Ingo Molnar <mingo@kernel.org>
- for s3c64xx
: use fixed IRQ bases to avoid conflicts on Cragganmore
- for exynos3250
: add cpuidle and AFTR mode support
: fix CPU1 hotplug
- for exynos SoCs
: add code for setting/clearing boot flag for cpuidle AFTR
: remove left over 'extra_save' and constify 'exynos_pm_data' array
: use static in suspend.c as per compiler suggestions
: use platform device name as power domain name
: add support for async-bridge clocks for pm_domains (exynos5420)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJVHDOIAAoJEA0Cl+kVi2xqIc0P/0x7bX76DHU01ATRWi4u+wRe
tPCjxeBpN/VfLb/x0JtFv6HHCGeGpgzEaYRHG7LHvX6F/oVldTuDr43aJximKG1k
NLG1NqczL4G6GrLABM3dQqWC88Jgrhfflqoq1y7M/fUhayOBjKcy0jrNIK1Qb+dp
3msyDeODyTSMIMIvufJLYW/kq0EVM7RMN9QUVGg+6YXZOuYs1nEa104PMElz8oEk
ntS14DYTZV/U5Nof+SK+6AYi+JN9ywnIv/NG0zjTF4kHEgqy+MRW7nRIKt4B7iSV
WT1i/AktTByEhhZlz3KTMyhrP/L0LxVqsc6COyrUHPj9yugWXcEmcoC7pOxni4sR
YWwDSCWkJyZ5PmzBG6tGLrEiUDlPng9qHCPXg5tI+ZRgli3IzKjPmUSB5onv3nT5
fHEH7uuhQ4D6MpNeCxb0KSDT6bvR3ghKZyIvn0X3sfRzGM1z4tDaG59FMlTc0DaX
jt56LHXfmqIomLNYRe3MihFHPtK0AB5z8SU//ebPFBIB+i3z3OLeQKNQkG6Zccuq
mhtlumGAe6xqPDNmN0KvnW2IJ9K+E35IH5M6goEddDK6xi6jCtyKGfL/CK6N+87C
rOIs08fg5tQ0i0KVzx0StbTMAOVfKMqGJrKeUuDb11fX8PUFEPYDl26QdSAcjkwQ
4Z6q42dLlxfWQOs5bF9N
=05kO
-----END PGP SIGNATURE-----
Merge tag 'samsung-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Merge "Samsung mach updates for v4.1" from Kukjin Kim:
- for s3c64xx
: use fixed IRQ bases to avoid conflicts on Cragganmore
- for exynos3250
: add cpuidle and AFTR mode support
: fix CPU1 hotplug
- for exynos SoCs
: add code for setting/clearing boot flag for cpuidle AFTR
: remove left over 'extra_save' and constify 'exynos_pm_data' array
: use static in suspend.c as per compiler suggestions
: use platform device name as power domain name
: add support for async-bridge clocks for pm_domains (exynos5420)
* tag 'samsung-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: allow cpuidle driver usage on Exynos3250 SoC
ARM: EXYNOS: add AFTR mode support for Exynos3250
ARM: EXYNOS: add code for setting/clearing boot flag
ARM: EXYNOS: fix CPU1 hotplug on Exynos3250
ARM: S3C64XX: Use fixed IRQ bases to avoid conflicts on Cragganmore
ARM: EXYNOS: Remove left over 'extra_save'
ARM: EXYNOS: Constify exynos_pm_data array
ARM: EXYNOS: use static in suspend.c
ARM: EXYNOS: Use platform device name as power domain name
ARM: EXYNOS: add support for async-bridge clocks for pm_domains
Signed-off-by: Olof Johansson <olof@lixom.net>
- for exynos3250
: add assigned clock parents for CMU nodes
- for exynos4412-odroid
: add eMMC reset line
- for exynos5250
: fixed typo for interrupt-cells
- for exynos5250-snow
: define stdout-path property
: represent bridge and panel connection
: enable wifi power-on and add cap-sdio-irq to wifi mmc node
- for exynos5250-spring
: define stdout-path property
- for exynos5420
: fixed typo for interrupt-cells
: add async-bridge clocks for gsc and disp1 PDs
- for exynos5420 boards
: Mux XMMCnDATA[0] pad correctly
- for exynos5420-odroidxu3
: add eMMC reset line
- for Peach boards
: add HS400 support and define stdout-path property
: add mclk entry and add WiFi module support
: represent bridge and panel connection
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJVHDABAAoJEA0Cl+kVi2xqaasP/04A2twJLhYzqobi9fdNOv+U
E14Z1qWv5XBnkkD4LewVCDTShVx+T6LDCAesJoaEcgK+ox8ZgcH4TlEslQ8pQdR5
3TjT1Tf/Qeldtri0Lb8jX9k7G6A+ogT1ywhMNUXTqLP3GFTgnIj/36MPlt22zYWp
w006UXDwYLrjFkX99lQr1XpDhPnTv3H+72ZPdDlRk59wxFnymQ0gb4Ong8bbKd56
0/35bw/fhHMTAtSVjVl6j5yblDl4NSh3y+T7Ftt59TKBBfhD0JB7VaT3OXmNqX52
mdhnT5MAK+l0LjW6a2xkbq+xgNAqSFhpX1d4RWwKheSa9aF2usCZnWxwzqCkLioa
v4O20gMlOkpq7pXduX+neJPgq1j1fls0ZlWKCTtgckmXCJQxdBkRYvuLeAz/QfGK
JZu/awQMLo8ebs8UaH1+mkpGsUzVzW5aGBw0ROH8N27R8xCmqujxMr9k6g9TRDTO
kFxIJAAsP1B/zEbvoI6LsPFPISBJjjjdOXClU72qrwNWuESWYsG71iI5PU6m2/bZ
Eq2qWa1dkOh3Lp/FVW6zXEGk60I1+ghd7VBC3GhbzDb4L5RMqeuRtD41DHKp4i67
UhymfzXuzyC1FDzI8qwySm2GApGhwN2mJwXc4bdOkABznytLJ5GumE6jc13806+/
mnUb7ksYakVIJyjVCE88
=Sz8u
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
Merge "Samsung DT updates for v4.1" from Kukjin Kim:
- for exynos3250
: add assigned clock parents for CMU nodes
- for exynos4412-odroid
: add eMMC reset line
- for exynos5250
: fixed typo for interrupt-cells
- for exynos5250-snow
: define stdout-path property
: represent bridge and panel connection
: enable wifi power-on and add cap-sdio-irq to wifi mmc node
- for exynos5250-spring
: define stdout-path property
- for exynos5420
: fixed typo for interrupt-cells
: add async-bridge clocks for gsc and disp1 PDs
- for exynos5420 boards
: Mux XMMCnDATA[0] pad correctly
- for exynos5420-odroidxu3
: add eMMC reset line
- for Peach boards
: add HS400 support and define stdout-path property
: add mclk entry and add WiFi module support
: represent bridge and panel connection
* tag 'samsung-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Fixed typo interrupt-cells for exynos5420 and exynos5250
ARM: dts: Add HS400 support for exynos5420 and exynos5800
ARM: dts: add async-bridge clocks to gsc power domain for exynos5420
ARM: dts: add async-bridge clocks to disp1 power domain for exynos5420
dt-bindings: add asynchronous bridge clock for exynos
ARM: dts: Define stdout-path property for exynos5250-spring
ARM: dts: Define stdout-path property for exynos5250-snow
ARM: dts: Define stdout-path property for Peach boards
ARM: dts: Add assigned clock parents to CMU node for exynos3250
ARM: dts: Add mclk entry for Peach boards
ARM: dts: Add WiFi module support for Peach boards
ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards
ARM: dts: add eMMC reset line for exynos5422-odroidxu3
ARM: dts: add eMMC reset line for exynos4412-odroid-common
ARM: dts: represent bridge and panel connection for exynos5420-peach-pit
ARM: dts: represent bridge and panel connection for exynos5250-snow
ARM: dts: Add cap-sdio-irq to wifi mmc node for exynos5250-snow
ARM: dts: Enable wifi power-on for exynos5250-snow
Signed-off-by: Olof Johansson <olof@lixom.net>
- update exynos-defconfig
: enable HDMI, CPUidle, ChromeOS EC chardev driver
and thermal emulation, Marvell WiFi-Ex, CPUfreq,
and support for NFS rootfs
: remove EXYNOS_THERMAL_CORE define
and disable IOMMU support until support it
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJVHCydAAoJEA0Cl+kVi2xqNTYP/3ciQM3vTSQSgvr8cG+1I0Gu
CtK+wY2t2KbFPd5rYoZ9E5NVC/E5KvY0iX+x58iKiWtWh93J269vVOqWM08kHekL
BCUXmKuFbVkNbzVev6/3krC79a89zMUf+D4m5pLxFzsmOXIOvHk5u7iHSbP0neq2
8gExFQHMbb2nwJl8rUMQNv8pD0kQXCxYNWQWyJr+Ec+zcu5JE532BWwFyG3xk+0W
TvBDDFTdCCySEOiOXu8aayPGYwx6QuPawoF+PFvi8qbJAtdl8Jt0LWkiajYsry3X
MMcDmXxbifHLlu8xb48EiLLzxh1OBbS/WBiMHNM86fNfyTXrQlZuUiIgiFShipig
rN6emtsdXMtGjhr99qiqCiK4Zb8nxDiVsNKh0fYiYVXxRoCIjmT5f1+3KAls8hs0
Ugz3VTL83lsJrs6mhPxpfqj+5lt57T3OhIyjvOZBSzxvrwWH5q0l2yLmfPKXqfC7
QKPDdpQwVv8OWZw25VSqyhROWAlS50XuGoSctcn+deKKQtIgtO1xSvEor2mddh0D
2BULXNgnjt3ttMXX4pQ2Ovk5eqERY1u+F6U1SogTSCOo6k+6fBTqn0a0fRGIpgYW
hCIxbmPyAWJVf6FGNwACByOVrpFtz+Jsaj4Ck52ow7NskIsKeRwkrgk1C5YCay5e
hVpWCNRR25U9ZyVcyCPY
=XAXR
-----END PGP SIGNATURE-----
Merge tag 'samsung-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/defconfig
Merge "Samsung defconfig updates for v4.1" from Kukjin Kim:
- update exynos-defconfig
: enable HDMI, CPUidle, ChromeOS EC chardev driver
and thermal emulation, Marvell WiFi-Ex, CPUfreq,
and support for NFS rootfs
: remove EXYNOS_THERMAL_CORE define
and disable IOMMU support until support it
* tag 'samsung-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: exynos_defconfig: Enable HDMI support
ARM: exynos_defconfig: Enable options to mount a rootfs via NFS
ARM: exynos_defconfig: Enable ChromeOS EC chardev driver
ARM: exynos_defconfig: Enable CPU idle
ARM: exynos_defconfig: Enable Marvell WiFi-Ex support
ARM: exynos_defconfig: Disable IOMMU support
ARM: exynos_defconfig: Enable support for cpufreq on Exynos SoCs
ARM: exynos_defconfig: Enable thermal emulation for Exynos TMU
ARM: exynos_defconfig: Remove CONFIG_EXYNOS_THERMAL_CORE define
Signed-off-by: Olof Johansson <olof@lixom.net>
- mostly trivial build fixes with random configurations
from Arnd Bergmann
for s3c24xx:
avoid a Kconfig warning and fix header file inclusions,
and fix building without PM_SLEEP and use SAMSUNG_WAKEMASK
for s3c64xx:
fix __initdata section mismatch and add I2C dependencies,
and fix building with PM_SLEEP
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJVHCusAAoJEA0Cl+kVi2xq3mUQAJBd7KaApfLWVubPOgwCDOcD
clJ/HuLxOsgvkut0EDVd1TVFpgpfFcYbjHTpEpDGDhwa/HtWkXYJe4yp88cE3usN
9HKW68GJXC4LU4Jz7x7MhRSrfx6f32evPcieh2JGXgHgnlP55fOVafBR8jsinJQj
YwZGW6nE/IlQMZOmJy5uNqzOS1Rbf6HbsnfrfDifzRBXeP+kX49P70BlV0P1t3DQ
8f2WokWGMzhE8mqEPYVQ5YrakXZjaRzDscxe5ZiFO6PJWDy6x5hxl+WOEMW4y1jP
BhQ3LonW6D8k1VCgV9hJvJ3VcmtHfOGpPJUQANODIC4MT82wp7TR6ztuG9cD2JfU
ZCMpiKhqO9K9jkuG8E1YppKK8qvb2aqVxqM4qOzBKwb540gCd+9NBsgQC6J/tSwK
E2aR6hH4KdRaXoNzywA3SP1I/gaLockA9w7g23dkn8Ds/OQLTrnoIfNH2MWG05HF
k9dEma95qhL9eEvSA6qUp402wDtk758lgdBTngivYeeJUtghcr9zxvoYWSvXtB/m
VO5xCWQ2aaTCaBCX9li3EbOzOL9fcb1TJ3o1MyRDKja3h2QKHG+ainskDpjhqBzj
KqpMLL6JDC7N0xkXp2p5YLFYU/mO9eE8WQ04I9j6xVFMq2mZ5Q57VW0C2YTTubOu
CFgx5TQXWPPzUCOnlKak
=Eywg
-----END PGP SIGNATURE-----
Merge tag 'samsung-fixes-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/fixes-non-critical
Merge "Samsung non-critical fixes for v4.1" from Kukjin Kim:
- mostly trivial build fixes with random configurations
from Arnd Bergmann
for s3c24xx:
avoid a Kconfig warning and fix header file inclusions,
and fix building without PM_SLEEP and use SAMSUNG_WAKEMASK
for s3c64xx:
fix __initdata section mismatch and add I2C dependencies,
and fix building with PM_SLEEP
* tag 'samsung-fixes-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C24XX: avoid a Kconfig warning
ARM: S3C24XX: fix header file inclusions
ARM: S3C24XX: fix building without PM_SLEEP
ARM: S3C24XX: use SAMSUNG_WAKEMASK for s3c2416
ARM: S3C64XX: fix __initdata section mismatch
ARM: S3C64XX: fix building without CONFIG_PM_SLEEP
ARM: S3C64XX: add I2C dependencies where needed
Signed-off-by: Olof Johansson <olof@lixom.net>
After 57a38effa5 (net: phy: micrel: disable broadcast for KSZ8081/KSZ8091)
the macb1 interface refuses to work properly because it tries
to cling to address 0 which isn't able to communicate in broadcast with
the mac anymore. The micrel phy on the board is actually configured
to show up at address 1.
Adding the phy node and its real address fixes the issue.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Johan Hovold <johan@kernel.org>
Cc: <stable@vger.kernel.org> #3.19
Signed-off-by: Olof Johansson <olof@lixom.net>
These changes have no influence on the kernel behavior (except
removing a warning message), but they allow to have a better
representation of the hardware.
- conform L2CC node with ePAPR specification by adding cache-level
- remove cpuclk resources overlapping coredivclk registers on Armada XP
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlUdAKQACgkQCwYYjhRyO9XKEgCgozRuaKXoWuFy8F2LUceCTEl0
y/cAoJOZjhbCTH81dyEFzJSXyUzXXWFX
=VUFU
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-4.1-3' of git://git.infradead.org/linux-mvebu into next/dt
Merge "ARM: mvebu: dt changes for v4.1 (round 3)" from Gregory Clement:
mvebu dt changes for v4.1 (part #3)
These changes have no influence on the kernel behavior (except
removing a warning message), but they allow to have a better
representation of the hardware.
- conform L2CC node with ePAPR specification by adding cache-level
- remove cpuclk resources overlapping coredivclk registers on Armada XP
* tag 'mvebu-dt-4.1-3' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level
ARM: mvebu: clk: remove cpuclk resources overlapping coredivclk registers on Armada XP
Signed-off-by: Olof Johansson <olof@lixom.net>
- Fix build breakage exynos cpuidle driver on !SMP
because it is coupled built-in so added check for SMP.
- Fix lid, power pin-functions and mmc node updates
for exynos5250-spring: Fixes commit ID 53dd4138bb
("ARM: dts: Add exynos5250-spring device tree")
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJVHCgYAAoJEA0Cl+kVi2xqOc0P/iRf+6vc1LLwbhJIjKnIkzqK
UEov7aWc4gBauP8oaQaaSV9DMShr0MVZlOgvQpjg5xYHYBcPAzVn+dR/vOxoIo5/
pQFMljNYDZONU+xkTGe8wFwCXk5ixBC8rhuGLCbqPXGa91zQrbRiEYPlFfsv4Req
dYtReh8+Uf8ATdqouvZ9FxP0q41LeeVthGvJwHy3folfom8T34UFtq38ecC10jqU
UlIgudYI5GOGBY1IZh3F0p+PTGug8BUTeapt4QcC6GlMDsB+ylvhRnk2cto85waD
2RBhyBMi1S419WT2G+h/Pr/Np9K7nwKiVD62eBoldYzUSOveufvMsDmtOTlxLumo
Jj+3/EDGMof74TeXeylZxr3wfj65yn9XAk2LQTQT8xh/wJjqZ1EHexKtikmdO84o
tSisyIBr7Bp6J2TREZm8CQbyPgY5ciyLlxT0mTWrWs7rt44ZELAv8nqyibfZ/ce4
TVTpdSWH8VPFteZrYXmbP+3va8RQvEyeg2mAtyEMJHX73UgYdxKt6bf66KypNDi7
zQVx26vDcbVCP2dQuwMO7LcIy9LyFnEEsN8ZqpRD+TSFkq/+fJPWSvH2kJr0wdUv
Nvxz0YkA+1E9agiFrh6WQzoWpubvngWUV4KCCyScB8Yta0py3uSqmu3IB0fHm4CJ
ALjWdQ9AKlEyd7o6rUxm
=pPV1
-----END PGP SIGNATURE-----
Merge tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Merge "Samsung 2nd fixes for v4.0" from Kukjin Kim:
- Fix build breakage exynos cpuidle driver on !SMP
because it is coupled built-in so added check for SMP.
- Fix lid, power pin-functions and mmc node updates
for exynos5250-spring: Fixes commit ID 53dd4138bb
("ARM: dts: Add exynos5250-spring device tree")
* tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Fix build breakage cpuidle on !SMP
ARM: dts: fix lid and power pin-functions for exynos5250-spring
ARM: dts: fix mmc node updates for exynos5250-spring
Signed-off-by: Olof Johansson <olof@lixom.net>
- Enable VFAT, Bluetooth and PCA953X GPIO expander support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJVGT+aAAoJEFBXWFqHsHzOmX4H/2SPkq4RO1aWtoydWiBBNdjl
eXwNH3eNU6Bt/pw+1yP2e2eb5fmKZtAXyWHl6ymQT4juZF6FVeddAWoVQrWZZTQb
i1sb5g2FoO7b+zGXftz2Rq29m5ioFT6aHdkS1np1ygy2HUwG4akzGUDB1bPZgFf8
q28DcmLNqwzqDpeKKBASkNo1yals+uiOl/u5uIOxJ21eP6Uqf8QW7vVSxg8zfawg
CKok/R4lwtwAclDeFZ9Kes937u8Czz+q3PbNHwjJfgdt0MtbQgu0GviYfTjhNArK
pATuDhNuJ4FnUKAidDwXvu5f7UZwmMamlinOifFoxRMtbN4/nGDwNSMfmWCoyQE=
=7uPF
-----END PGP SIGNATURE-----
Merge tag 'imx-defconfig-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/defconfig
Merge "ARM: imx: defconfig updates for 4.1" from Shawn Guo:
The i.MX defconfig updates for 4.1:
- Enable VFAT, Bluetooth and PCA953X GPIO expander support
* tag 'imx-defconfig-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx_v6_v7_defconfig: Enable Bluetooth support
ARM: imx_v6_v7_defconfig: Add CONFIG_GPIO_PCA953X
ARM: imx_v4_v5_defconfig: Add VFAT support
ARM: mxs_defconfig: Add VFAT support
Signed-off-by: Olof Johansson <olof@lixom.net>
- An error handling improvement on imx-weim bus driver
- A number of imx6q clock tree update around MIPI support
- Add support for i.MX6 GPU/VPU power domain
- Enable SMP_ON_UP build for Vybrid
- Let MXC_DEBUG_BOARD depend on 3-stack (3DS) boards
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJVGO1MAAoJEFBXWFqHsHzOjGcH/jFjIi46ieB0z79KVp/Ni8dL
5w5Myfamyl0Eas/NS0iuAZ2kRkvK4kFxZOfBpWSQc6mQeS93RhydXx+CvzcuzNJr
lnDiBWFZfWLYxkb4KiKoTd6szXDwZXM3N5Dj0oO/2RRme29GE/G9tCKR92YU8ZI4
KvDiBFb0hsP0IcB5Y/9p8ETwjTnpKXdZ2sS91K9oNh5vzrnv0sANxtShmNHq08hX
0XLOFTMF99NMmeCH5L8h01rl9L2nz4dXOpXafjlAdZUEf1h7jCqBM8is2R4VkWuF
mfVmCrucmn2RNwQwT3Rj+qQH7hApOcPdoXjg9Z8tqDfSxuZYlMg9xWQ7t9zJlsw=
=oHN4
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "ARM: imx: soc changes for 4.1" from Shawn Guo:
The i.MX SoC changes for 4.1:
- An error handling improvement on imx-weim bus driver
- A number of imx6q clock tree update around MIPI support
- Add support for i.MX6 GPU/VPU power domain
- Enable SMP_ON_UP build for Vybrid
- Let MXC_DEBUG_BOARD depend on 3-stack (3DS) boards
* tag 'imx-soc-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: depend MXC debug board on 3DS machines
ARM: imx6: gpc: Add PU power domain for GPU/VPU
Documentation: Add device tree bindings for Freescale i.MX GPC
bus: imx-weim: improve error handling upon child probe-failure
ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate
ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate
ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate
ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock
ARM: imx6q: clk: Add the video_27m clock
ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition
ARM: vf610: use SMP_ON_UP for Vybrid SoC
Signed-off-by: Olof Johansson <olof@lixom.net>
- Convert i.MX25 to be a DT only platform and remove the code that is
only used by non-DT support
- A couple trivial cleanup on iomux-v3 code
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJVGOsvAAoJEFBXWFqHsHzO8tAH/RN7+it0BDHhznppwonYx3OI
hTdkgvZ9WwMg9X5MelEgyvrtgSiPB9SvpkUiW7eV8/FK7ZhKbD86YuWHiQ7AOTYg
hy87sbrJaJtNcsLpLzvDUZWpLa0zSLW0GGuwevNuxC1M8vljwZI5i0ONEGCSf7Bf
N1DawR39AHi9Z997NIfnUwNV3VSDV/YZd6znxZh6UocFbWvRKpRZWeexdHPQPlXE
Y/HaVbPHDpKxH1nhlAvmmsum5/uTGdVGRXAtTPRgJJeJiXDquwKVKIypiR503mE/
04v837w1R/xwmp7cOTRUHnjphTsGjqTKcMc8FDsS8FoFzWa34kVicUDL2vZEykA=
=0TsA
-----END PGP SIGNATURE-----
Merge tag 'imx-cleanup-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/cleanup
Merge "ARM: imx: cleanup for 4.1" from Shawn Guo:
The i.MX cleanup for v4.1:
- Convert i.MX25 to be a DT only platform and remove the code that is
only used by non-DT support
- A couple trivial cleanup on iomux-v3 code
* tag 'imx-cleanup-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx_v4_v5_defconfig: Remove CONFIG_MACH_MX25_3DS
ARM: mx25: Remove imxdi_rtc platform code
ARM: mx25: Remove "mx25.h" header file
ARM: mx25: Remove static memory mapping
ARM: mx25: Retrieve IIM base from dt
ARM: mx25: Remove mx25_clocks_init()
ARM: mx25: Remove platform code support files
ARM: mx25: Convert to a dt-only platform
ARM: imx25: Remove eukrea mx25 board files
ARM: mx25: Remove mach-mx25_3ds board file
ARM: imx: Fix trivial typo in comments
ARM: imx: Kconfig: Fix grammar in help text
ARM: imx/iomux-v3: allow pad_list to be const
Signed-off-by: Olof Johansson <olof@lixom.net>
Disable CPU Idle on Armada 38x
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlUc/VsACgkQCwYYjhRyO9VRMQCgm649m2RGKpuIHIfrrUY5Ml9P
sYEAn3B+ExgeILErBXde/N3gGlu84U4Q
=qI89
-----END PGP SIGNATURE-----
Merge tag 'mvebu-fixes-4.0' of git://git.infradead.org/linux-mvebu into fixes
Merge "ARM: mvebu: fixes for v4.0" from Gregory Clement:
mvebu fix for 4.0
Disable CPU Idle on Armada 38x
* tag 'mvebu-fixes-4.0' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Disable CPU Idle on Armada 38x
Signed-off-by: Olof Johansson <olof@lixom.net>
Needed in several Chromebook models such as the Tegra-based ones.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Needed in several Chromebook models such as the Tegra-based ones.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This brings the DevFreq framework in and builds the ACTMON driver that
on Tegra124 will scale the external memory clock based on current load.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
A bunch of changes to improve support on the Nyan Big (Acer Chromebook
13). These enable the trackpad and make the WiFi card work. Changes to
the userspace-exposed name of the soundcard are required for a better
audio experience.
Support for Nyan Blaze (HP Chromebook 14) is added. It is very similar
to Nyan Big and therefore can enjoys many of the above improvements.
Since the EMC driver can now be used to scale the frequency at which
external memory is clocked, corresponding EMC frequency tables are added
for Jetson TK1 and the Nyan boards.
The Jetson TK1, Beaver and Nyan boards now also use generated pinmux
data, which makes it easier to keep it in sync with the data provided by
syseng.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJVGSCcAAoJEN0jrNd/PrOhy3kP/j5j4AEYnSxIAPx52U3Yv7j4
HvqDpCx3vC3oJrRAFvHlv5v9FUx1EWpbV7GjyTP/kmbTAJdP6USRVFEs//+2p3tO
dzBhZFDpygkIZOzVlO7C2o4bW9OVUiPbYeuZi0T1AgTvOzylzhdk3U0sMI0XgNZp
QLha3gx4Kgs0j2GeTDZjy7iHgku1OwuBRgg0l2QdMl2fq3Cy7cJub5FkVR/T51yS
y6dJSypS+4gE/x1GRS67U5OADeGl0+Rmd1TI1Hxab292fG6jcE+gtLz+gFboay4e
9F+fOU42JSD1O+5w1byMYW1WqpzZ8stIvs4end6PBteVaMFLEj7uWHuCnMbjZr2J
YXbhFRT1lNJiEtPoLR3xPZsiGSG8Jf/ANkb/7fozposHke4zW/bEe8+lq94x0O0+
iqhY/0EdMsCiPTkXZ9OsG15nSvXzSAC9w9TzLyQzTL/+cCZGSEO5wpCL36ixSB7a
sE5VFDq1WLN25r3jrCKcESy2PxhaRciW99D92SomAqvJBmHpzZ0GsfG7Nt6VkQ/f
W+ilkULDzpeTesN6Ajx1G78yNUQXV+Gfm3WhsC7xsG7mf0Uo+0E8uAA5OzaVNkxP
+JJ/F4wsKbPnbPlFuh4/CPwZHk8Dd8Q7+aTzcTDQxcJncGzv/fW3jpdS1vg7jr5L
BXC55v7bM6a/d2gGhsO6
=yFLx
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.1-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
Merge "ARM: tegra: Device tree changes for v4.1-rc1" from Thierry Reding:
A bunch of changes to improve support on the Nyan Big (Acer Chromebook
13). These enable the trackpad and make the WiFi card work. Changes to
the userspace-exposed name of the soundcard are required for a better
audio experience.
Support for Nyan Blaze (HP Chromebook 14) is added. It is very similar
to Nyan Big and therefore can enjoys many of the above improvements.
Since the EMC driver can now be used to scale the frequency at which
external memory is clocked, corresponding EMC frequency tables are added
for Jetson TK1 and the Nyan boards.
The Jetson TK1, Beaver and Nyan boards now also use generated pinmux
data, which makes it easier to keep it in sync with the data provided by
syseng.
* tag 'tegra-for-4.1-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Add EMC timings to Nyan Blaze device tree
ARM: tegra: Add EMC timings to Nyan Big device tree
ARM: tegra: Add EMC timings to Jetson TK1 device tree
ARM: tegra: Add EMC to Tegra124 device tree
ARM: tegra: Add Tegra124 ACTMON support
of: Add binding for NVIDIA Tegra ACTMON node
ARM: tegra: nyan: The WiFi card is kept powered during suspend
ARM: tegra: nyan: Add gpio-restart node
ARM: tegra: nyan: Set maximum frequency for SPI flash
ARM: tegra: Use generated pinmux data for Nyan Big
ARM: tegra: Use pwrseq-simple for the wifi in Nyan
ARM: tegra: Add node for trackpad in Nyan boards
ARM: tegra: Add DTS for the nyan-blaze board
ARM: tegra: Move generic parts out of the nyan-big DT
ARM: tegra: Change model of sound card in Nyan Big
ARM: tegra: Use generated pinmux for Beaver board
ARM: tegra: Import latest Jetson TK1 pinmux
Signed-off-by: Olof Johansson <olof@lixom.net>
Make the Juno .dts robust against potential reordering of the CPU nodes
by adding an explicit interrupt-affinity property to the PMU node. While
we're at it, fix the PMU interrupts numbers too.
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Paul Walmsley <paul@pwsan.com>:
OMAP hwmod data changes for AM43xx and DRA7xx for v4.1
Add support for the AM43xx HDQ/1-wire driver and fix the GPTIMER data
for DRA7xx.
Note that I do not have AM43xx nor DRA7xx boards, and cannot test these
patches on those platforms.
Basic build, boot, and PM test logs are available at:
http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.1/20150324185246/
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVFdXLAAoJEBvUPslcq6VzpncQAK9+IrlLZm2XpoIzPNovDEMN
yQFyTDLLBl+o6SgUgMLn8yWaJmCJpsmSUBnqV50z/vIcuwMHu4Ih43vU/htMp5dH
fRu0v3qkxvjcfe9t1n08xVGleaHZ0xYbB7lm3WlRC+wCoaHiyIu49vijPrpVQY5C
2TKLw+7T5gqTqjTabdL9jItmi8QgTc9ajSoyWXz2YL63ss2I/utBxFCk6iGL4mln
GlL/wfQ8Vp+h82JTRDIDsYF7xMmXrvDDkBZoQjxF3B3NOf1TsXaPcOMqaSXVdRXC
ArK7dMMmhX+cXbaK7I4YWqUIRy5XOP8Uk2c4k+q69yeJhpGN+aPzTo/tTGf/hNSo
H3ydYKZEF/ZgqMswvDb5k2FCNPfQLSJ+fQ/hrjBrzbtsR1goDW0o/wcsweWIHS8u
G16Bo03jYce6WMR0FZSS5DmILMyFd4327ZShQmuYNJeyhY3PzoPc1bnxNzc6fukH
VbAx49WFTMXD2lK63NkmDgj90pPm8tgn4yhgLuH24n8gf988nuVnBBz+2fE8pSow
W1hmKnVBMX2psM9KTmQbSE9QlI5y0prLYheCfj+AE3No94ZjdihgYecINGBzCxtQ
nNuzdLIQFsnS4VQ/ATYNmLK9NGgbIWT/2Zm1124JUv9ecRjpFf574ybwwKYMqtXz
BcBLkLk3wYKjvAdeBH5Z
=LgBG
-----END PGP SIGNATURE-----
Merge tag 'v4.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Merge "omap soc changes for v4.1" from Tony Lindgren:
SoC related changes for omaps. Mostly hwmod related changes via
Paul Walmsley <paul@pwsan.com>:
OMAP hwmod data changes for AM43xx and DRA7xx for v4.1
Add support for the AM43xx HDQ/1-wire driver and fix the GPTIMER data
for DRA7xx.
Note that I do not have AM43xx nor DRA7xx boards, and cannot test these
patches on those platforms.
Basic build, boot, and PM test logs are available at:
http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.1/20150324185246/
* tag 'v4.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4
ARM: DRA7: hwmod: Add data for GPTimers 13 through 16
ARM: omap-device: add missed callback for suspend-to-disk
ARM: OMAP2: hwmod: AM43XX: Add hwmod support for HDQ-1W
Signed-off-by: Olof Johansson <olof@lixom.net>
This is mostly to enable errata 798181 and thermal support for dra7,
configure ocp2scp for am437x, remove dead code for OMAP4_ERRATA_I688
and fix build warnings for omap1510 only config.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVFc/qAAoJEBvUPslcq6VzopMQAN8i0DkYqm8cM8mK/UitjG7o
+vfGo2ik3sk7AidU7vnjLdQFJOxo8T9LI9+OGr2YJ9JmbzkH1H2QsGVF/MYTaox7
i/Eb9MEPFuu9ek3iKAUVVwPTHi0ft3/W5EzwHIdKHHz6UGjrVuBNxyInNXJiVm4y
mAragQWKQGwtSEqCpdSDgkzBh0VOPo9BSpa/1QXOsYLarOurAUNPKgbc6VoSzF9d
nkvbwlXhVobvVIv5Qyhef9CHssRGL6pEgvJIoNVcqgBzjrPgat4l+qYE4ns/FEMp
LjbE2p3pr2ODECC5xETWFqtKXlqywj1+4HtEcGOD6L52fBdpE5yshOEa81goHpI2
WMu4l4qus+u92g/012sOMH/KT0lTDPj1OTnjtgxonpmi12oJjWtKy/WQsussBfIU
ttAiCZCoEguKrWAFiYZ4A3x5cUHFiC0Xn99h0p6I6fc434ORy6T5uBotgjGfQuBr
YkpS8ok6wNkYWQUpxji0dO0MkUjf2VbQXWuFfhs5sK2yiwv6cDNK5a8rpDvgls1H
JMwRxqqX7jL9d+yYXban6PZv2BKSpOzJTOVEdvpFUUYMHtRoNMqkAIuhtKtWWclc
W9CnZCx2CBvfaz+Hs7IACWy7KhdhYj5xjiBgSpykJVWHmHU3HugbY27LJnxTFd2n
ElZlY1NH1iZPjeAl3Q43
=Uqd0
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.1/fixes-0' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical
Merge "omap non-urgent fixes for v4.1" from Tony Lindgren:
Fixes for omaps that were not considered urgent enough for the -rc cycle.
This is mostly to enable errata 798181 and thermal support for dra7,
configure ocp2scp for am437x, remove dead code for OMAP4_ERRATA_I688
and fix build warnings for omap1510 only config.
* tag 'omap-for-v4.1/fixes-0' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA7: Enable Cortex A15 errata 798181
ARM: dts: am57xx-beagle-x15: Add thermal map to include fan and tmp102
ARM: dts: DRA7: Add bandgap and related thermal nodes
bus: ocp2scp: SYNC2 value should be changed to 0x6
ARM: dts: am4372: Add "ti,am437x-ocp2scp" as compatible string for OCP2SCP
ARM: OMAP2+: remove superfluous NULL pointer check
ARM: OMAP4: remove dead kconfig option OMAP4_ERRATA_I688
MAINTAINERS: add OMAP defconfigs under OMAP SUPPORT
ARM: OMAP1: PM: fix some build warnings on 1510-only Kconfigs
Signed-off-by: Olof Johansson <olof@lixom.net>
This series reworks some of the CCI-400 PMU code so that it can be used
on both ARM and ARM64-based systems, without the need to boot in secure
mode on the latter. This paves the way for CCI-500 support in future.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCgAGBQJVFWAiAAoJELescNyEwWM0pK8IALUinCT+Ec/Oi5WwGJaLgQgw
exlDFAcmml0xisxglGL7eHcvNBs/j4wFD37mqDUszrGW3jrM+Ex+/cvUzWIlEyZl
LjG99ZF2j51LFxDHMgpRwg1aD/NNQsQjwsuHHdCr+NHB5R2C0M4umsgX6Kt6/PE4
95LOnnjBOx4FkMOG9mZElzldUlqnhWd6drjQ9qZQar9VVVewfbR1LH/xQhjrCL0w
nwRzJwYj1LnLFO0hBVUAJSfvYltMF9PxBEx0FkyzN7QcuP1tLQ25NmGEvarHP6iZ
XpvTZ7akzButyUQbvz/kf6a0agPNUv1HHEqh7/Zddvgm//+p8nEBORuJ/cC6g1E=
=UHCi
-----END PGP SIGNATURE-----
Merge tag 'arm-perf-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/drivers
Merge "arm-cci PMU updates for 4.1" from Will Deacon:
CCI-400 PMU updates
This series reworks some of the CCI-400 PMU code so that it can be used
on both ARM and ARM64-based systems, without the need to boot in secure
mode on the latter. This paves the way for CCI-500 support in future.
* tag 'arm-perf-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux:
arm-cci: Fix CCI PMU event validation
arm-cci: Split the code for PMU vs driver support
arm-cci: Get rid of secure transactions for PMU driver
arm-cci: Abstract the CCI400 PMU specific definitions
arm-cci: Rearrange code for splitting PMU vs driver code
drivers: cci: reject groups spanning multiple HW PMUs
+ Linux 4.0-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standalone power collapse (SPC) idle state (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add ARM common idle states device bindings for cpuidle support for APQ
8084.
Support Standalone power collapse (SPC) idle state (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add ARM common idle states device bindings for cpuidle support for APQ
8974/8074.
Support Standalone power collapse (SPC) idle state (power down that does
not affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Model the Qualcomm Technologies LPASS hardware for the ipq806x SOC.
Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Acked-by: Banajit Goswami <bgoswami@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
PMA8084 have 2 SPMI devices per physical package. Add their
configuration nodes and include them in boards which are using
AQP8084 based chipset.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
PM8841 and PM8941 have 2 SPMI devices per physical package.
Add their configuration nodes and include them in boards
which are using 8x74 based chipset.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add SPMI PMIC Arbiter configuration nodes for APQ8084 and MSM8974.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the node for the LPASS clock controller found on a few qcom
SoCs so that the clock driver can probe.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
[sboyd@codeaurora.org: Added apq8064 and msm8960 nodes]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds TCSR support for use by the GSBI to automatically
configure ADM CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add initial device tree support for Qualcomm APQ8016 SBC Evaluation board.
This board is also referred to as the DragonBoard 410c.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add initial device tree support for Qualcomm MSM8916 SoC and MTP8916
evaluation board. At the current time we only boot up a single processor.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
* Increase MMC_BLOCK_MINORS to 32 since qcom platforms have more than
16 partitions
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: GPGTools - https://gpgtools.org
iQIcBAABCgAGBQJVFYb7AAoJEF9hYXeAcXzBKcEQANqLRQvljpkQIvLFg4ztL2z+
5kGkGMsuEzFTorZ4ma8dxZal8fBLhRMVYs6kDYEy8+yIRBmoysAA0ylQ/ZZQCXTi
lBqDypDA8v3xJg8u+2oD5MITZ1N8M7QowqTg96R1Fw7vf8alVsWwjR5SFCRfP2j2
L34LuKQp3IXUyMTBWFZB3cZAxPorsj3inBobRVLHj27BmIevc5hw+KCOJNDp5KEx
4ZBOfGGovIYO2mNq2b15RY6Y+aIQwVuDHb6rKj/Pti4Q2mCwmNR6sUfeUXm5C1JC
d2B9o5g+xpLT+L2+j08SbdxzUgG3DBwe6LyMmDR3BxrS3SIeiQK+RNqUSqpEoj1N
MOAK7AzKwU4ONDgJU85KTlxTCY+sEg6IfkMnvGUM2RioqMfbnqMnIiCKkG6e72Pj
T817mfLChv938VngooP7vsWivyigJSSVP61+vn/zsQVuEQuqKR/VHI160IUdGS8L
h/PMyDtqJwl5A77UPfr6/weyX+NQBqaXpfwHWLWSxF4MT/INvo6PKrRa4btIuPos
C4qYKew2vaiymPGvsniywv4F6rsmq+B9YA0E2ciYnN3jXbB13ic4pLUy1bxvrWM+
HNHEk0zegf2hiwYFePGk/yNvhlWCuNin9SiqnzCi+Y9axpzyFmXdJiH6yyEWp4y6
4TS1dKXFP8HuMO8bQUiW
=zxOh
-----END PGP SIGNATURE-----
Merge tag 'qcom-defconfig-for-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/defconfig
Merge "qcom defconfig changes for 4.1-1" from Kumar Gala:
Qualcomm ARM Based defconfig Updates for v4.1-1
* Increase MMC_BLOCK_MINORS to 32 since qcom platforms have more than
16 partitions
* tag 'qcom-defconfig-for-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
ARM: qcom: Increase MMC_BLOCK_MINORS in defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
data instead of platform data from Eliad Peller <eliad@wizery.com>:
- Add device-tree support to the wlcore (wl12xx/wl18xx) driver.
- Update the current users to use the bindings instead of pdata-quirks.
- Finally, remove the deprecated wl12xx_platform_data struct
Note that da850 board file code that still uses the platform data,
but we have da850.dtsi that can be used instead. So it was decided
that we should try to remove the wl12xx support from the da850
board file as suggested by Sekhar Nori <nsekhar@ti.com>. As it's
the last patch in the series, the last patch can be simply reverted
if needed.
As this series touches quite a bit of arch code, it was suggested
by Kalle Valo <kvalo@codeaurora.org> that the whole series should
be merged via the arm-soc tree.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVEyqpAAoJEBvUPslcq6VzXFgP/2iNBoDmg3Zu+FR/waaVOD/k
iOUrT7ZU2Db4dWgprAwKTByiNg1PZ7cPVF3ekKR2j870YWNG8RTKrN1//t4tRCJv
gwSDNYJan8uCd54fgopi4mFC2/YhwzwH76ow1+DGw3+QoEBu9X0e/63uWNSQXTnE
ldNA+IiXp68DvCj5Xn649TdZTCNeNcAfQGt5MItwFuIAU+1hP9jIbEqFmC+HbFOb
xsn66ziTXTu8aLGR3Pkf2PTpJXEiKbuX11Un1BZfgJ5GJp+aSa8zAGX+rYXhTwv6
Cw+jtJffHbuA4RPdqLPPAWgPhmNfM4D+kLdu/N8iEi72Lsoq2VgLi2IgE5g60Bq9
7AxgAvZImvE3X8lSxeyyT4VfD7xVuRfzqbCXd/RJteZogRME7nxWrm2q32e/IDo9
EdWsOMTA2jNG7W0UN8ChX5aexb2n1LqxABLnKnEHuvV/qvw33O6QtMmFyzB+t2Pr
BpX7H2hwFFU2daF1xRTp/zAJIavsADAgnwco47NZlrBNfkyOH12b0YOuUgKOK8mi
/0zDi1NpCdU+nDgWynnlMBbpk3NMTVLE2IkHNDJ7pJ9Eagf6KDw/yJrhiRAJyJu8
CRTTdyEX1lBbPznYz7j95JD3Rw0g+TWg+pMlVpj6zaJQcWl0pWphXpoPYE1UZZTR
VJWeFrbVptL3mBXoKWyp
=Nr1k
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.1/wl12xx-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Merge "wireless wl12xx and omap device tree changes for v4.1" from Tony
Lindgren:
Wireless and omap changes to make wl12xx driver to use device tree
data instead of platform data from Eliad Peller <eliad@wizery.com>:
- Add device-tree support to the wlcore (wl12xx/wl18xx) driver.
- Update the current users to use the bindings instead of pdata-quirks.
- Finally, remove the deprecated wl12xx_platform_data struct
Note that da850 board file code that still uses the platform data,
but we have da850.dtsi that can be used instead. So it was decided
that we should try to remove the wl12xx support from the da850
board file as suggested by Sekhar Nori <nsekhar@ti.com>. As it's
the last patch in the series, the last patch can be simply reverted
if needed.
As this series touches quite a bit of arch code, it was suggested
by Kalle Valo <kvalo@codeaurora.org> that the whole series should
be merged via the arm-soc tree.
* tag 'omap-for-v4.1/wl12xx-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
wlcore: remove wl12xx_platform_data
ARM: dts: add wl12xx/wl18xx bindings
wlcore: add device-tree support
dt: bindings: add TI's wilink wireless device
wl12xx: use frequency instead of enumerations for pdata clocks
wlcore: set irq_trigger in board files instead of hiding behind a quirk
+ Linux 4.0-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
* Removal of mach-msm and associated drivers cleanups that have been
ack'd by associated maintainers
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: GPGTools - https://gpgtools.org
iQIcBAABCgAGBQJVFYYJAAoJEF9hYXeAcXzBqZkQAOnZShQ3iLgo5Btn0wGLMN2X
AiUqztk0iHV+R94ahpAmkCF5iYUYWotViacGZ7JA+8TVef1m1JosTKzjswS0736l
copG345v4JijBMVks6Jg5HX6MZZqmIKZKyBNhIqYl8dA84NRClno6La3iwjbLsDv
9suavM3ylgUTFpJdXZynz0AhOlbFeiUTYXYCPgSu6OSjYSs1JYcyGo/4cnaviR6w
WkkAnlgplx9qTCPGwuPvGLlFL632kezIERwElUEoSNz7GavR3rFwLlyOfToQyjMU
t6mTlVKwVvdS0dLSCAN076XxTpbPpaRlnH+0Ij1F6dhaPDjdJ+7I+TOMYidrgfbE
exNLftXFdT05pt2e/ThRPJWsS6y2SuOhxqvjwRwsQs1ozSt5s9t9w/Jrb4kShbaC
gcbjqKw+tFijzgF+KGz9aQ84gLTyxaFMd120o/JDXscgodeXZWSUrPoWLt1ilKlN
9gwA26cOF/vLOUUM1qCGG/gTHPOfFVObj0DbW43PqKhYdrpHBBRbLxf8zF0w1fmQ
vLq8nNuY84hViJLuDb2lXnM1Z1yH5QAXm2mh7uMU3z7W4sDM8e2U3e2rasFAL0SN
FmpuxqlnK+QglC9foT6mq8rZLQytIysmkzsn3Zg0A6lEvP76OIi9cHqlZyv0T174
j9FupW91klhS4bG4sx50
=rBCl
-----END PGP SIGNATURE-----
Merge tag 'qcom-cleanup-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/cleanup
Merge "qcom cleanup changes for 4.1" from Kumar Gala:
General cleanups for MSM/QCOM for 4.1
* Removal of mach-msm and associated drivers cleanups that have been
ack'd by associated maintainers
* tag 'qcom-cleanup-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
mmc: Remove msm_sdcc driver
gpio: Remove gpio-msm-v1 driver
ARM: Remove mach-msm and associated ARM architecture code
+ Linux 4.0-rc3
Signed-off-by: Olof Johansson <olof@lixom.net>
Nothing really standing out here, just a few options to enable in the defconfigs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVEyXYAAoJEBx+YmzsjxAgrFQQALpZ2O17Z7EyH0V/RszYLllP
a1YXgj+b5gT3OaD9RHZ73/dKKA7kohkgzWn88CTGzt7J3dfsPwzaLXPOj2xAJffK
0INE00XP2b8RHykTXR4zZp1+PUA+qpvZLFYfWa8BYBMMn9OEVXztoLptXR+lpz3V
2zzr5y9npV709P8SIaT4XzLSCgQAD9h0RM4F3E5qRUSJKsYxbCSAi2S/h2bvlu6C
R2uo8ktUuVZs6jaaWUWczD+KS5No+P/r30VkPSZp1xU4gpXdWVIhNpj5fU409p5b
PaNcEUnGDp2yrZzwMBBXrpxKYlySo8iMy6si/XmWKhbPURVfMW3SqXxFSOFdOuTj
z5iMZYiJvzIsMrvj8qlyaCFGlg9axEzZiJ2UMJdrYfoKjNSZvXELoInGeDqJY2LA
iqPrX2JGvdZAU/VOyagrBY5/TsupaWAS+kI6iLvBiRvNt0s8i84K0+EHTxVT9VNv
yrod3jNw9caNWPQdsmwiWC9SpCCfmv7w9Z2dhW14AgnPTRNxHrRtTijGIktdwvzo
Fby3jdaZDzowF7Iv2+veKa5Ja5k2ipVcv3jVA1uWaMd3h1SgZApPJhTd9useucmk
5JSS9bh8pzwBFyjcGVXa0LPNyFVWZU2fAM++7n56VFTVGyot4zXSxfjIX+cNPjPj
lEtjoAYudb8Oxr5iEVrQ
=99ES
-----END PGP SIGNATURE-----
Merge tag 'sunxi-defconfig-for-4.1' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/defconfig
Merge "Allwinner defconfig changes for 4.1" from Maxime Ripard:
Nothing really standing out here, just a few options to enable in the defconfigs
* tag 'sunxi-defconfig-for-4.1' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi_defconfig: increase the number of maximum number of CPUs to 8
ARM: multi_v7_defconfig: Enable CONFIG_PHY_SUN9I_USB
ARM: sunxi_defconfig: Enable CONFIG_PHY_SUN9I_USB
Signed-off-by: Olof Johansson <olof@lixom.net>
The custom suspend callback is removed for this change. The extra call
to exynos_cpu_power_up(() that was present at the end of exynos_suspend()
is now relocated to the cpu_is_up callback.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Currently the cpu argument validity check uses a hardcoded limit of 4.
The DCSCB configuration data provides the actual number of CPUs and
we already use it elsewhere. Let's improve the cpu argument validity
check by using that information instead.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
All backends are reimplementing a variation of the same CPU reference
count handling. They are also responsible for driving the MCPM special
low-level locking. This is needless duplication, involving algorithmic
requirements that are not necessarily obvious to the uninitiated.
And from past code review experience, those were all initially
implemented badly.
After 3 years, it is time to refactor as much common code to the core
MCPM facility to make the backends as simple as possible. To avoid a
flag day, the new scheme is introduced in parallel to the existing
backend interface. When all backends are converted over, the
compatibility interface could be removed.
The new MCPM backend interface implements simpler methods addressing
very platform specific tasks performed under lock protection while
keeping the algorithmic complexity and race avoidance local to the
core code.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Support only for ETF, FUNNEL, STM are included currently.
Support for ETM, TPIU and the replicator linked to it are not included in
this version patch.
Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
* Remove default cpuidle driver, it does not appear to serve any purpose
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVEgOQAAoJENfPZGlqN0++9GQQAK32yBvDVGxsxs4Sf0+BeXsQ
qiVoRsqhNIDtHmonGwpQAtpBxLbKiKUgTUXsT3BbX7YOgGwv0QxsiZnP6jsn0CR9
+cqylFHmSpC14hBfVSl59JKwOOeJ5C46xlnfB0Kf6h/HPBhDR83wPxGMrkAiYKd1
XsibuWhzDHZT5MpMXCuTzcWSWeC7Ss+BeimmT+5+pU6WzNx2gQGIYJstqcoYXdRH
ssUzGt83jUYxwAzh9pd4TsPQqqaPteB0t6AoMUWr3K3RAii2TwUTPrfoxfxBWLMS
mq1im3oH6VZdjc9vzFwlHR54C8/LOEDx3amdyJXPPShb1ZY59Fyk+FsL5GWsb1sO
ro7WJWBupSUFO+DD0IPMzoR6CZTim//lImbmS6FFd3x1KP8e64NEhPHl1D335eUj
w2yR/WCKDChxZ2n5eu3kpaIXGIhsevfjeIOJhgClnScgK3IHDNvQGOq0UPhk/YKI
Ggn13hI1VsV7+leZnt8uWaJ/rQfXfcf6EVmPhrgaPbOMXVThzrQJmPCxs57D4Qj/
KCcDtDnZTYgfxMsUK4/QzV7Fa+KLTwuLnDd/SZ1cmGDhDbnTMtAxTiTNqE/q4C7+
Gy1SBlFbarEIv3Ch5/LOkTjHrZQEec9GncxDF2PzAPoFq9XmEqbnUpnMJxqcwaRs
l68w1O/jQWHNVppl1tau
=wZzt
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-cleanup3-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Merge "Third Round of Renesas ARM Based SoC Cleanup for v4.1" from Simon
Horman:
* Remove default cpuidle driver, it does not appear to serve any purpose
* tag 'renesas-soc-cleanup3-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: cpuidle: Remove the pointless default driver
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Broadcom Device Tree changes for 4.1 #3" from Brian Norris:
This pull request contains changes to the BCM7445 reference DTS files from
Brian:
- making a clock-frequency property decimal instead of hexadecimal
- adding the irq0 interrupt controller node to make the reference DTS bootable
again
* tag 'arm-soc/for-4.1/devicetree-part-3' of http://github.com/broadcom/stblinux:
ARM: dts: brcmstb: add IRQ0 controller
ARM: dts: brcmstb: un-hexify clock frequency
Signed-off-by: Olof Johansson <olof@lixom.net>
* Fixed WAITMONITORINGTIME programming to be based on
GPMC_CLK instead of GPMC_FCLK. The GPMC clock divider
programming is fixed for both synchronous and asynchronous
modes.
* Allow GPMC's children of default bus type to be populated in
the device tree.
* Improved DEBUG output data and format.
* Prevent writing 1 into reserved bits of GPMC_CONFIG7.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJU+Z36AAoJENJaa9O+djCTdvUP/3a4AxX5cUavSsu9YYMJirL7
9JxUETrQfjkpRLrXDtahchn/nqnBESMMss992ipWBLyT1idQu81I2wztMM6KuQnc
iuL8h8lQCctjEBAkKxWkZVORq60NcgRhBivAClUHxxpobA8MnChRwHmrJI8aPGxp
/XKogeg5aa99NyRgQo7t4fMg8/KZWyUGtVf21wXhfwyhuV+dP8vUQMvaxXjQqXJ2
r936x1fOT+hA48sScRbcCGFaATmxoNN5Tx8+lfCqXv2JXUt1Y+7FXUtnkiC3nc6Y
JLZ9rKeBv45VLf7TMlGJBlQj3o971CahrlxXv3P3i/G/ALoJE1Xyuqto4dJ474N/
hU7OlPyrSZF9J9z/e0uhpteuk7KHq6mgZ7HGh+ytKlFrTocOqTlbO0L/zRvOXXuB
Aajcs1PbpG5j0Znha0sYyj33y5UbKnpTxlydffLA7r3wiNUr3fI9+bR5uOsnu+yF
OwgJLCeymp1DiqGx3gupTvkJLJJxb7wjMUncGhXt3pRKJEQHBWekOZnI7v4S3tXE
r6HjvKoe+ZdQQyUaCb17jOMZ0FLOSsT3XcIqq1xOMzhxP7tSRRQet3hkdL4CgP1E
fedp0FintqpUfzBQkRn6JY/UMR2mCCalPMaOF7L/sa5wOWRSjSoXOHa5w6lHQJVB
fWZR4/msDvBrVnxuKAci
=wtGZ
-----END PGP SIGNATURE-----
Merge tag 'gpmc-omap-for-v4.1' of git://github.com/rogerq/linux into next/drivers
Merge "OMAP-GPMC driver fixes for v4.1" from Roger Quandros:
* Fixed WAITMONITORINGTIME programming to be based on
GPMC_CLK instead of GPMC_FCLK. The GPMC clock divider
programming is fixed for both synchronous and asynchronous
modes.
* Allow GPMC's children of default bus type to be populated in
the device tree.
* Improved DEBUG output data and format.
* Prevent writing 1 into reserved bits of GPMC_CONFIG7.
* tag 'gpmc-omap-for-v4.1' of git://github.com/rogerq/linux:
ARM OMAP2+ GPMC: fix programming/showing reserved timing parameters
ARM OMAP2+ GPMC: fix WAITMONITORINGTIME divider bug
ARM OMAP2+ GPMC: calculate GPMCFCLKDIVIDER based on WAITMONITORINGTIME
ARM OMAP2+ GPMC: always program GPMCFCLKDIVIDER
ARM OMAP2+ GPMC: change get_gpmc_timing_reg output for DTS
ARM OMAP2+ GPMC: fix debug output alignment
ARM OMAP2+ GPMC: add bus children
ARM OMAP2+ GPMC: don't undef DEBUG
ARM: OMAP2+: gpmc: make gpmc_cs_get_name() static
ARM: OMAP2+: gpmc: Fix writing in gpmc_cs_set_memconf
Signed-off-by: Olof Johansson <olof@lixom.net>
- add support for Performance Monitor Unit on most of mvebu SoCs
- add nas2big support
- add support for USB3 port On Armada 385 AP
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlUL6VsACgkQCwYYjhRyO9Vm/wCfZNIo3l1U82ietdSE8zuVWq1U
A2gAmQHeLLV6izood0nm9/AvvcMHPpI5
=rtR1
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-4.1-2' of git://git.infradead.org/linux-mvebu into next/dt
Merge "ARM: mvebu: dt changes for v4.1 (round 2)" from Gregory Clement:
mvebu dt changes for v4.1 (part #2)
- add support for Performance Monitor Unit on most of mvebu SoCs
- add nas2big support
- add support for USB3 port On Armada 385 AP
* tag 'mvebu-dt-4.1-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: armada-385-ap: Enable USB3 port
ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC
ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC
ARM: mvebu: Enable Performance Monitor Unit on Armada XP/370 SoCs
ARM: Kirkwood: add DT description for nas2big
Signed-off-by: Olof Johansson <olof@lixom.net>
- add perf support in mvebu_v7_defconfig
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlUL6CAACgkQCwYYjhRyO9XHCACgiDr25bMPW6sxghz6LNXP9fbv
6z4AnjYvd/kefOzNeAJFrVLJyt2I24lV
=TxRJ
-----END PGP SIGNATURE-----
Merge tag 'mvebu-defconfig-4.1-2' of git://git.infradead.org/linux-mvebu into next/defconfig
Merge "ARM: mvebu: defconfig changes for v4.1 (round 2)" from Gregory Clement:
mvebu defconfig changes for v4.1 (part #2)
- add perf support in mvebu_v7_defconfig
* tag 'mvebu-defconfig-4.1-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Enable perf support in mvebu_v7_defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
* Consolidate the pm code for R-Car Gen2
* Correct SYSCIER value for r8a7790 and r8a7791 SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVC2/9AAoJENfPZGlqN0++QAoP/ijqzdLRJznv0Td4sBVwcNgP
L3YOAwaMM4xG527QwETdz7KT1LnbNMROp/MbBrmdDQM2lfz7um8oFAdKcxe+7RLM
GAJiH61RZfrPEzjOhwXoIMyAMPUR42rSI1dl78nMDg4pjKACurwpXjLPxNLMGiTa
v09iJA/JYcrFNlTB+wWQiskln3rq87wVSmD27pVQo1p0TH1tn+yS1DBVbqzb9M+Y
d1DVvYhsjx1tjz6yzP6+C/rkXgNex4FCMsd2QrLOVXS+FkU1OklFEyaPMP6Tz5Y0
CXgvByWjTt8Sz8hcPBhpVr7rg7BPZ0EX0SDD9NvdLCAGlXtxpVfh0YadupCkF/I2
9rmwG0B3IL66d2Z4erH7H3hhurC+hnSeuXDeVzGyJGAQ/Cky3Qg5KLEJz1hFYoLu
EY6kob48Ar3sXO4NFvY60C11+xJKrCFT1l/f5ZG1AgG8D1LjFGeUcp04AM0LE6pD
haMv5a7FTUDsp9bK9278btZuSHxgap8pnFpvHvXwVDfWDcFDfzgtPc2M0ifhxf82
MbyIE5BGg+36ri5Opw8SAZ1Fjl/AymlJu2w5+bcKQxkjID7N2HD5YrdTfhkFA4ID
uGA1XldCrCUYlziOty82Pe8ZLz2PkZjgSvcN5juYLMX2VU/Ug6AKPLfbWEtN8WmO
rpwEwmmQ6j6eooVQXBzk
=Y+v1
-----END PGP SIGNATURE-----
Merge tag 'renesas-pm-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Merge "Renesas ARM Based SoC PM Updates for v4.1" from Simon Horman:
* Consolidate the pm code for R-Car Gen2
* Correct SYSCIER value for r8a7790 and r8a7791 SoCs
* tag 'renesas-pm-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Consolidate the pm code for R-Car Gen2
ARM: shmobile: r8a7791: Correct SYSCIER value
ARM: shmobile: r8a7790: Correct SYSCIER value
Signed-off-by: Olof Johansson <olof@lixom.net>
We want to get omap3 moved over to device tree only based booting.
These three board-*.c files seem to be inactive, so let's attempt
to drop them now rather than later. With these dropped, we have
omap3 device tree conversion status in a known state. Then we know
that we have .dts support for the remaining omap3 board-*.c files,
or it's being worked on.
By dropping these files now, we can simply revert them if really
needed for the next few merge cycles if we run into suprises.
Reverting things later on will not be so easily done.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVCzwBAAoJEBvUPslcq6VzDzkP/iy7ayrSC9nyam6l3nx2NXUJ
IHAobxYgZbqcJabAGGDq41Ko+XurupJy+k92PyGSkw/kMBxl8myr1+okqVXPvlcP
gUa33GDCjWrrnVAW2wxQpHGWbxuFdJgWCqe8TttG2/hlF2A4piYs11ImskckkSLk
Ad2n1I8FV5NxKNt0USloXQmAQK20y85JywAL4LrzIX7mBOuAPvL1CyPfCvVRd0Au
htcVxrEeCg+D72PloOVnnddYXRc5Gjl1iq47lVZEhUpt99bhSwN2YpW05sbo+Gq8
AG/Y+v5HV0rCtmpzTPclsn7gaVkT948sij/PFbVJmK7nxpIH0AsaTfkjjB4ccwrB
lsZThdGK+ewWWrMas41A7TAtUwFF7Zi/WIfNYNjRy0biHA7XwiibVMjq4zjWuyCO
ZAeFho5xtEAEM4XJpcqM/UFhu1inGW0aiELvNCk7LJuJDM+MHiGeDVzmZyB2Qv8n
V7uIYI8gN/+X9byD162lOjN3cXLAhpCWRUnOmV9EgamaUNKrrEVCmSEyHASUs7A2
4fexhVEhDS1qqSlw1tK/c3Fz6IQYKGKjB58mi4x/r5CZd4e0sVNC3HqAVEuGXNk4
P8qMC77pA1vWg3gG42qLEhlEFpbZ1CHH40NRj/K/gkd21GVJaf/BI+nW5Z7IPH2F
4Zd0NLDnlOi2SxpCxlXb
=IWkd
-----END PGP SIGNATURE-----
Merge tag 'v4.1-legacy' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
Merge "omap legacy boot clean-up for v4.1" from Tony Lindgren:
Drop three omap3 legacy board-*.c files
We want to get omap3 moved over to device tree only based booting.
These three board-*.c files seem to be inactive, so let's attempt
to drop them now rather than later. With these dropped, we have
omap3 device tree conversion status in a known state. Then we know
that we have .dts support for the remaining omap3 board-*.c files,
or it's being worked on.
By dropping these files now, we can simply revert them if really
needed for the next few merge cycles if we run into suprises.
Reverting things later on will not be so easily done.
* tag 'v4.1-legacy' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Remove legacy support for omap3 TouchBook
ARM: OMAP3: Remove legacy support for devkit8000
ARM: OMAP3: Remove legacy support for EMA-Tech Stalker board
Signed-off-by: Olof Johansson <olof@lixom.net>
loadable modules.
Note that I'll do patches for armv7_defconfig for these at some
point too once we're happy with omap2plus_defconfig to avoid
extra churn on the defconfig files.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVCzo8AAoJEBvUPslcq6Vzm8sP/3NN2+AOZJGEc6v2a+Kcj+OM
4SKTgnMy4k3Lyys49EdHKSviPEr/5F68rQ4SMZtTBk9+AkTI0C+NBGlgVdQDiTcC
m1CN0V696/TkPfNM7pMa2AM8fvI0Ic+3s++9L+k7g0ffHOtsgJ3RUThqpSWplcWJ
9IQzZcSMBpjn+bZz9dOdqfnTOf+djm3xyMijN0pu6ukm7xLZBwxt4cXapHhcqFJY
uxE8TyQ0gkN2Gfb7N5TJ6yX2K3GddkaQ3UGSJEylDTE0naYGkOjYfY41/zLLiNq8
w+P422P9VEZf0gt+N21odeRo8o1WwBywkbVgpsDtbbAelLrQcr3SxrIg2Rptbnou
PUuhspRX3NJbfQf/u4mz04MlhoN/K5ysrOCF7OSFS5vQYwQYJPvnhffxc6hO5mjs
OfS7lDzzcwTcmJZhfxPdP9+CazLPwU9OjlQXFdEoov4YoJaGSdQJxolYLFmheiDt
fWMlhD1ZbiQbBCNqgyWxMzGCmNywQqwc0wc/6Ne4MqnHXl/BbZ2EisIbGpX31S6h
D/vnpxCm2MQ8MervMo2hUoQ29KK5uc777MzTJo/JjhcbPjciD/FdkXrVdf6SQJGw
9azbW8xtkC4GjiZKDo4lmUvokkh3Iyxb2s/WVJEFN7CTOOr/XW/0gN2a1vcPkdkg
5qvocYhO4jucaejva5/P
=59fx
-----END PGP SIGNATURE-----
Merge tag 'v4.1-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/defconfig
Merge "omap defconfig changes for v4.1" from Tony Lindgren:
Few omap2plus_defconfig updates to add commonly used drivers as
loadable modules.
Note that I'll do patches for armv7_defconfig for these at some
point too once we're happy with omap2plus_defconfig to avoid
extra churn on the defconfig files.
* tag 'v4.1-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: omap2plus_defconfig: Enable n900 modem as loadable modules
ARM: omap2plus_defconfig: Update bluetooth options
ARM: omap2plus_defconfig: Enable leds-pwm
ARM: omap1_defconfig: drop obsolete Kconfig symbols
arm: config: omap2plus_defconfig: switch over to LZMA compression
ARM: omap2plus_defconfig: Enable EXTCON_GPIO_USB
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add support for ChiliSOM
- Add support for OpenPandora
- Add support for BeagleBoard NAND
- Enable crypto devices for omap3 devices
- Add bindings for omap3 camera support
- Updates for am437x and dra7x and dm816x SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVCzjKAAoJEBvUPslcq6VzRvgQAJRyAIX43yBmmLG9cgHu3aJ2
Apbqj1wHnpPLIvu/bfAGU5xSZw1c9OqVn7X+PTlgKvtImpFoqqFko9LYxvSkdQjY
X+AYySjCty/mnwaMus14/viVnS4iHLeLD9eUqh+6pZ+Dhj2A44ZJaeBNONTNG6kY
fSy8hA9UJefDVD6nBKDoDPXDZNOjjQZL8yH57QkYp4zaeCFep+Y6uoPEw8HeQ3eg
InU7VVbHLogZq6ViMjUuVgxkNIcnBzZP4lZSH9JRDumHkSsujbkLqqMjumwIh1tZ
yXjsxYAnkBh6OvtuDBzvuqqig0XKnDMZgeau1ejBl44V8pkvA4/xDO9iXBgOPxJq
sQqfQrgPRk3lAkUKgvQBHh4q3CZYux5jTUTZmnWLOVb61XySXhKiLR9lISplqu7f
R+7bfNZ6oifkwzKXAatFLIG95cuAmvZ4EHkAPGsIPF6uEkvHMkfQ2B0LEak04+ek
UJKAuxOj439ue9e+PXr6QSM6nJnegYsIIRWs1BcnozrzmVOql4zDLLd+Lf/h3O0L
iA2dtOByRzUtaRki3koyNDzJ783h6I3xXMnt0VEY/zucsT9v56ht3kdpZIkVkxK+
D4Z5zK3kZgVeAwF6IPXNwxtWWEEvzzGhnu/ZvhtI756HHX++gMi7DQYODegbxpoi
0nzHxHEEvpisXF3li4Ba
=BU88
-----END PGP SIGNATURE-----
Merge tag 'v4.1-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Merge "omap device tree changes for v4.1, part1" from Tony Lindgren:
Device tree related changes for omaps:
- Add support for ChiliSOM
- Add support for OpenPandora
- Add support for BeagleBoard NAND
- Enable crypto devices for omap3 devices
- Add bindings for omap3 camera support
- Updates for am437x and dra7x and dm816x SoCs
* tag 'v4.1-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (27 commits)
ARM: dts: Update Nanobone dts file
ARM: dts: n950, n9: Add primary camera support
ARM: dts: omap3: Add DT entries for OMAP 3 ISP
Documentation: DT: Add bindings for omap3isp
ARM: dts: Remove files omap34xx-hs.dtsi and omap36xx-hs.dtsi
ARM: dts: omap3-tao3530: Include directly omap34xx.dtsi
ARM: dts: n900: Enable omap sham and include directly omap34xx.dtsi
ARM: dts: n9/n950: Enable omap crypto support
ARM: dts: Remove PIN_INPUT for dm816x McSPI
ARM: dts: Add cppi41 support for dm816x MUSB
ARM: dts: Fix typo for dm816x usb0_pins
ARM: dts: dra7x-evm: beagle-x15: Fix USB Peripheral
ARM: dts: am57xx-beagle-x15: Do not include the atl header
ARM: dts: DRA7: Remove ti,timer-dsp and ti,timer-pwm properties
Documentation: omap-twl4030: Move ti,codec property to optional
ARM: dts: omap3: Remove all references to ti,codec property
ARM: dts: omap3-beagle: Add NAND device
ARM: dts: AM4372: update hdq compatible property
ARM: dts: omap3-pandora: add DM3730 1 GHz version
ARM: dts: omap3-pandora: add OMAP3530 600 MHz version
...
Signed-off-by: Olof Johansson <olof@lixom.net>
When building a legacy (non-multi) platforms and if the ARCH_AT91 config option
is enabled there is a build error. We need AT91 to depend on multi-platform
core type options.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Pull x86 fixes from Ingo Molnar:
"Misc fixes: a SYSRET single-stepping fix, a dmi-scan robustization
fix, a reboot quirk and a kgdb fixlet"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
kgdb/x86: Fix reporting of 'si' in kgdb on x86_64
x86/asm/entry/64: Disable opportunistic SYSRET if regs->flags has TF set
x86/reboot: Add ASRock Q1900DC-ITX mainboard reboot quirk
MAINTAINERS: Change the x86 microcode loader maintainer
firmware: dmi_scan: Prevent dmi_num integer overflow
This adds support for the N900's accelerometer to
the Nokia N900 DTS file.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Éric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Keeping drivers related to HW tracing on ARM, i.e coresight,
under "drivers/coresight" doesn't make sense when other
architectures start rolling out technologies of the same
nature.
As such creating a new "drivers/hwtracing" directory where all
drivers of the same kind can reside, reducing namespace
pollution under "drivers/".
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The coresight-default-sink configuration option has been
removed from the framework. As such remove it from DT and bindings.
Signed-off-by: Kaixu Xia <xiakaixu@huawei.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Most CoreSight blocks are 64-bit ready. As such move configuration
entries from "arch/arm/Kconfig.config" to the driver's subdirectory
and source the newly created Kconfig from architecture specific
Kconfig.debug files.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Richard Weinberger
Linus Torvalds
Andrey Ryabinin
Ralf Baechle
Vineet Gupta
Mischa Jonker
Heiko Carstens
Max Filippov
Michael Ellerman
Ard Biesheuvel
Arnd Bergmann
Rafael J. Wysocki
Guenter Roeck
Mark Brown
Ingo Molnar
Al Viro
Denys Vlasenko
Dave Olson
Anton Blanchard
Sukadev Bhattiprolu
Cyril Bur
Sam bobroff
Daniel Axtens
Thomas Gleixner
Jason Cooper
Markos Chandras
Rafał Miłecki
Huacai Chen
Niklas Cassel
James Hogan
John Crispin
Ganesan Ramalingam
Aaro Koskinen
Alexander Sverdlin
Greg Kroah-Hartman
Russell King
Mike Travis
Ley Foon Tan
Aravind Gopalakrishnan
Florian Fainelli
Bjorn Helgaas
Thomas Petazzoni
Wanpeng Li
Nadav Amit
Radim Krčmář
Arseny Solokha
Eugene Korenevsky
Paolo Bonzini
Maciej W. Rozycki
Steven Rostedt (Red Hat)
Dave Young
David S. Miller
Borislav Petkov
Brian Gerst
Alexandre Belloni
Olof Johansson
Nicolas Ferre
Tomeu Vizoso
Will Deacon
Lina Iyer
Kenneth Westfield
Ivan T. Ivanov
Kumar Gala
Andy Gross
Nicolas Pitre
Chunyan Zhang
Sebastian Reichel
Mathieu Poirier
Kaixu Xia
Borislav Petkov