Commit Graph

195 Commits

Author SHA1 Message Date
Martin Michlmayr 586dcf279b [ARM] Kirkwood: Add support for QNAP TS-119/TS-219 Turbo NAS
Add support for the QNAP TS-119 and TS-219 Turbo NAS devices.

Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-23 16:12:38 -04:00
Martin Michlmayr a441891f9d [ARM] Kirkwood: More consistency regarding MPP naming
With the exception of UART0, all MPP names are uppercase.

Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-23 14:45:24 -04:00
Martin Michlmayr 6574e001b4 [ARM] Kirkwood: Hook up I2C
Hook up I2C on Marvell Kirkwood.  Tested on a QNAP TS-219 which has
RTC connected through I2C.

Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-23 14:42:00 -04:00
Lennert Buytenhek e84665c9cb dsa: add switch chip cascading support
The initial version of the DSA driver only supported a single switch
chip per network interface, while DSA-capable switch chips can be
interconnected to form a tree of switch chips.  This patch adds support
for multiple switch chips on a network interface.

An example topology for a 16-port device with an embedded CPU is as
follows:

	+-----+          +--------+       +--------+
	|     |eth0    10| switch |9    10| switch |
	| CPU +----------+        +-------+        |
	|     |          | chip 0 |       | chip 1 |
	+-----+          +---++---+       +---++---+
	                     ||               ||
	                     ||               ||
	                     ||1000baseT      ||1000baseT
	                     ||ports 1-8      ||ports 9-16

This requires a couple of interdependent changes in the DSA layer:

- The dsa platform driver data needs to be extended: there is still
  only one netdevice per DSA driver instance (eth0 in the example
  above), but each of the switch chips in the tree needs its own
  mii_bus device pointer, MII management bus address, and port name
  array. (include/net/dsa.h)  The existing in-tree dsa users need
  some small changes to deal with this. (arch/arm)

- The DSA and Ethertype DSA tagging modules need to be extended to
  use the DSA device ID field on receive and demultiplex the packet
  accordingly, and fill in the DSA device ID field on transmit
  according to which switch chip the packet is heading to.
  (net/dsa/tag_{dsa,edsa}.c)

- The concept of "CPU port", which is the switch chip port that the
  CPU is connected to (port 10 on switch chip 0 in the example), needs
  to be extended with the concept of "upstream port", which is the
  port on the switch chip that will bring us one hop closer to the CPU
  (port 10 for both switch chips in the example above).

- The dsa platform data needs to specify which ports on which switch
  chips are links to other switch chips, so that we can enable DSA
  tagging mode on them.  (For inter-switch links, we always use
  non-EtherType DSA tagging, since it has lower overhead.  The CPU
  link uses dsa or edsa tagging depending on what the 'root' switch
  chip supports.)  This is done by specifying "dsa" for the given
  port in the port array.

- The dsa platform data needs to be extended with information on via
  which port to reach any given switch chip from any given switch chip.
  This info is specified via the per-switch chip data struct ->rtable[]
  array, which gives the nexthop ports for each of the other switches
  in the tree.

For the example topology above, the dsa platform data would look
something like this:

	static struct dsa_chip_data sw[2] = {
		{
			.mii_bus	= &foo,
			.sw_addr	= 1,
			.port_names[0]	= "p1",
			.port_names[1]	= "p2",
			.port_names[2]	= "p3",
			.port_names[3]	= "p4",
			.port_names[4]	= "p5",
			.port_names[5]	= "p6",
			.port_names[6]	= "p7",
			.port_names[7]	= "p8",
			.port_names[9]	= "dsa",
			.port_names[10]	= "cpu",
			.rtable		= (s8 []){ -1, 9, },
		}, {
			.mii_bus	= &foo,
			.sw_addr	= 2,
			.port_names[0]	= "p9",
			.port_names[1]	= "p10",
			.port_names[2]	= "p11",
			.port_names[3]	= "p12",
			.port_names[4]	= "p13",
			.port_names[5]	= "p14",
			.port_names[6]	= "p15",
			.port_names[7]	= "p16",
			.port_names[10]	= "dsa",
			.rtable		= (s8 []){ 10, -1, },
		},
	},

	static struct dsa_platform_data pd = {
		.netdev		= &foo,
		.nr_switches	= 2,
		.sw		= sw,
	};

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Gary Thomas <gary@mlbassoc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-03-21 19:06:54 -07:00
Russell King 7d83f8fca5 Merge branch 'master' of git://git.marvell.com/orion into devel
Conflicts:

	arch/arm/mach-mx1/devices.c
2009-03-19 23:10:40 +00:00
Russell King be093beb60 [ARM] pass reboot command line to arch_reset()
OMAP wishes to pass state to the boot loader upon reboot in order to
instruct it whether to wait for USB-based reflashing or not.  There is
already a facility to do this via the reboot() syscall, except we ignore
the string passed to machine_restart().

This patch fixes things to pass this string to arch_reset().  This means
that we keep the reboot mode limited to telling the kernel _how_ to
perform the reboot which should be independent of what we request the
boot loader to do.

Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-19 16:20:24 +00:00
Nicolas Pitre e96c33d9ed [ARM] Kirkwood: SheevaPlug LED support
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-15 22:09:09 -04:00
Nicolas Pitre 3ec0d47427 [ARM] Kirkwood: SheevaPlug USB Power Enable setup
Ideally, the default should be set to 0 and let the EHCI driver turn
it on as needed.  This makes USB usable in the mean time.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-15 22:08:33 -04:00
Shadi Ammouri 4640fa606b [ARM] Kirkwood: Marvell SheevaPlug support
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-03-15 22:04:54 -04:00
Nicolas Pitre 5b99d53483 [ARM] Kirkwood: register internal devices in a common place
The RTC and the two XOR engines are internal to the chip, and therefore
always available since they don't depend on a particular board layout.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-02-26 22:55:59 -05:00
Nicolas Pitre 249cbfa3f5 [ARM] Kirkwood: remove unneeded includes from board setup files
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-02-26 21:35:59 -05:00
Nicolas Pitre 3c2613dbbc [ARM] Kirkwood: add NAND support to the DB88F6281 board
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-02-26 21:19:51 -05:00
Nicolas Pitre 8235ee009c [ARM] Kirkwood: SDIO driver registration for DB6281 and RD6281
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-02-26 20:22:26 -05:00
Lennert Buytenhek 12f4815b42 [ARM] Kirkwood: enable both XOR engines on the 6281 RD board
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2009-02-19 22:28:47 -05:00
Nicolas Pitre 0100defd28 [ARM] Kirkwood: MPP initialization code
This allows for board support code to set up their MPP config if the
bootloader didn't do it all or did it wrong.  This also allows to
register usable GPIOs.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-02-19 22:27:52 -05:00
Nicolas Pitre fd4b9b3650 [ARM] 5401/1: Orion: fix edge triggered GPIO interrupt support
The GPIO interrupts can be configured as either level triggered or edge
triggered, with a default of level triggered.  When an edge triggered
interrupt is requested, the gpio_irq_set_type method is called which
currently switches the given IRQ descriptor between two struct irq_chip
instances: orion_gpio_irq_level_chip and orion_gpio_irq_edge_chip. This
happens via __setup_irq() which also calls irq_chip_set_defaults() to
assign default methods to uninitialized ones.  The problem is that
irq_chip_set_defaults() is called before the irq_chip reference is
switched, leaving the new irq_chip (orion_gpio_irq_edge_chip in this
case) with uninitialized methods such as chip->startup() causing a kernel
oops.

Many solutions are possible, such as making irq_chip_set_defaults() global
and calling it from gpio_irq_set_type(), or calling __irq_set_trigger()
before irq_chip_set_defaults() in __setup_irq().  But those require
modifications to the generic IRQ code which might have adverse effect on
other architectures, and that would still be a fragile arrangement.
Manually copying the missing methods from within gpio_irq_set_type()
would be really ugly and it would break again the day new methods with
automatic defaults are added.

A better solution is to have a single irq_chip instance which can deal
with both edge and level triggered interrupts.  It is also a good idea
to switch the IRQ handler instead, as the edge IRQ handler allows for
one edge IRQ event to be queued as the IRQ is actually masked only when
that second IRQ is received, at which point the hardware can queue an
additional IRQ event, making edge triggered interrupts a bit more
reliable.

Tested-by: Martin Michlmayr <tbm@cyrius.com>

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-17 22:37:09 +00:00
Nicolas Pitre 13731d1a2f [ARM] 5357/1: Kirkwood: add missing ge01 tclk initialization
Otherwise the mv643xx_eth driver will assume 133 MHz which is incorrect.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-01-08 16:29:41 +00:00
Nicolas Pitre 6e5c11a1c0 [ARM] 5359/1: Kirkwood: fix compilation error
Commit ba84be2338 broke the build.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-01-08 16:29:40 +00:00
Lennert Buytenhek 4c21343005 [ARM] Kirkwood: implement GPIO and GPIO interrupt support
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-12-20 12:26:57 -05:00
Russell King 72aaf09fda Merge git://git.marvell.com/orion into devel 2008-12-13 09:12:51 +00:00
Ronen Shitrit 37787e449b [ARM] Kirkwood: properly handle the WAN port on newer RD88F6281 boards
On newer versions of the RD88F6281 board, the WAN port is connected to
its own ethernet port on the CPU, via a separate PHY, whereas on older
versions of the board, it is connected to one of the PHYs in the
ethernet switch.  In the RD8F6281 setup code, detect which version of
the board we are running on, and instantiate the ethernet ports and
switch driver accordingly.

Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-12-11 16:39:08 -05:00
Ronen Shitrit d15fb9efe9 [ARM] Kirkwood: allow instantiating the second ethernet port
The 88f6192 and 88f6281 Kirkwood SoCs support two ethernet ports.
Add the platform glue that will allow board support files to
instantiate the second ethernet port.

Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-12-11 16:39:08 -05:00
Ronen Shitrit fb6f552930 [ARM] Orion: add the option to support different ehci phy initialization
The Orion ehci driver serves the Orion, kirkwood and DD Soc families.
Since each of those integrate a different USB phy we should have the
ability to use few initialization sequences or to leave the boot loader
phy settings as is.

Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
2008-12-04 01:28:14 -05:00
Russell King dcea83adc6 [ARM] Hide ISA DMA API when ISA_DMA_API is unset
When ISA_DMA_API is unset, we're not implementing the ISA DMA API,
so there's no point in publishing the prototypes via asm/dma.h, nor
including the machine dependent parts of that API.

This allows us to remove a lot of mach/dma.h files which don't contain
any useful code.  Unfortunately though, some platforms put their own
private non-ISA definitions into mach/dma.h, so we leave these behind
and fix the appropriate #include statments.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-29 18:42:40 +00:00
Nicolas Pitre b5ee900258 [ARM] remove a common set of __virt_to_bus definitions
Let's provide an overridable default instead of having every machine
class define __virt_to_bus and __bus_to_virt to the same thing.  What
most platforms are using is bus_addr == phys_addr so such is the default.

One exception is ebsa110 which has no DMA what so ever, so the actual
definition is not important except only for proper compilation.  Also
added a comment about the special footbridge bus translation.

Let's also remove comments alluding to set_dma_addr which is not
(and should not) be commonly used.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28 15:36:49 +00:00
Nicolas Pitre fd55cd3d3a [ARM] 5321/1: Kirkwood: fix typo in Makefile
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-23 19:58:19 +01:00
Lennert Buytenhek dcf1cece14 [ARM] Orion: instantiate the dsa switch driver
This adds DSA switch instantiation hooks to the orion5x and the
kirkwood ARM SoC platform code, and instantiates the DSA switch
driver on the 88F5181L FXO RD, the 88F5181L GE RD, the 6183 AP GE
RD, the Linksys WRT350n v2, and the 88F6281 RD boards.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-10-19 14:29:05 -04:00
Linus Torvalds 7cc4e87f91 Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
  [ARM] 5300/1: fixup spitz reset during boot
  [ARM] 5295/1: make ZONE_DMA optional
  [ARM] 5239/1: Palm Zire 72 power management support
  [ARM] 5298/1: Drop desc_handle_irq()
  [ARM] 5297/1: [KS8695] Fix two compile-time warnings
  [ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
  [ARM] pxa: allow multi-machine PCMCIA builds
  [ARM] pxa: add preliminary CPUFREQ support for PXA3xx
  [ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
  [ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
  [ARM] pxa/zylonite: add support for USB OHCI
  [ARM] ohci-pxa27x: use ioremap() and offset for register access
  [ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
  [ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
  [ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
  [ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
  [ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
  [ARM] pxa: simplify DMA register definitions
  [ARM] pxa: make additional DCSR bits valid for PXA3xx
  [ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
  ...

Fixed up conflicts in
	arch/arm/mach-versatile/core.c
	sound/soc/pxa/pxa2xx-ac97.c
	sound/soc/pxa/pxa2xx-i2s.c
manually.
2008-10-11 10:09:45 -07:00
Ronen Shitrit 4360bb4192 [ARM] Kirkwood: add support for L2 cache WB/WT selection
Feroceon L2 cache can work in eighther write through or write back mode
on Kirkwood. Add the option to configure this mode according to Kconfig.

Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-09-25 16:29:21 -04:00
Lennert Buytenhek 2d0c9e735a [ARM] Kirkwood: allow configuring mbus window for on-chip sram
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-09-25 16:27:22 -04:00
Ronen Shitrit 3a64ebc9ce [ARM] Kirkwood: remove uart1 init calls for boards that don't expose uart1
Remove uart1 init calls for boards that use the physical pins onto
which the UART1 signals are multiplexed for different purposes.

Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-09-25 16:27:22 -04:00
Ronen Shitrit b2b3dc2fc4 [ARM] Kirkwood: add support for newer SoC models
Add support to the Kirkwood port for newer device models and silicon
revisions.  Instead of looking at the DEVICE_ID register, the device
version is now determined by looking at the PCI-Express device ID and
revision registers, as it is done for orion5x, and this information
is used to determine the TCLK frequency, again, as it is done for
orion5x.

Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-09-25 16:27:21 -04:00
Ronen Shitrit 79d4dd77f0 [ARM] Kirkwood: prepare for runtime-determined timer tick rate
Currently, kirkwood uses a hardcoded timer tick rate of 166 MHz, but
the actual timer tick rate varies between different members of the SoC
family.

This patch prepares for runtime determination of the timer tick rate.

Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
2008-09-25 16:27:21 -04:00
Lennert Buytenhek 144f814a43 [ARM] Kirkwood: wire up ethernet error interrupt
Wire up the ethernet port's error interrupt so that the
mv643xx_eth driver can sleep for SMI event completion instead of
having to busy-wait for it.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-09-25 16:26:44 -04:00
Lennert Buytenhek ac840605f3 mv643xx_eth: remove force_phy_addr field
Currently, there are two different fields in the
mv643xx_eth_platform_data struct that together describe the PHY
address -- one field (phy_addr) has the address of the PHY, but if
that address is zero, a second field (force_phy_addr) needs to be
set to distinguish the actual address zero from a zero due to not
having filled in the PHY address explicitly (which should mean
'use the default PHY address').

If we are a bit smarter about the encoding of the phy_addr field,
we can avoid the need for a second field -- this patch does that.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-09-05 06:33:59 +02:00
Lennert Buytenhek 18365d181f [ARM] Kirkwood: instantiate the orion_spi driver in the platform code
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-09 15:38:18 +02:00
Saeed Bishara 09c0ed2e6e [ARM] Kirkwood: Instantiate mv_xor driver
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-09 15:17:29 +02:00
Lennert Buytenhek 6f088f1d21 [ARM] Move include/asm-arm/plat-orion to arch/arm/plat-orion/include/plat
This patch performs the equivalent include directory shuffle for
plat-orion, and fixes up all users.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-09 13:44:58 +02:00
Russell King a09e64fbc0 [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-07 09:55:48 +01:00
Russell King 4fb8af10d0 Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixes 2008-08-07 09:55:03 +01:00
Russell King be50972935 [ARM] Remove asm/hardware.h, use asm/arch/hardware.h instead
Remove includes of asm/hardware.h in addition to asm/arch/hardware.h.
Then, since asm/hardware.h only exists to include asm/arch/hardware.h,
update everything to directly include asm/arch/hardware.h and remove
asm/hardware.h.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-07 09:40:08 +01:00
Lennert Buytenhek 81600eea98 mv643xx_eth: use auto phy polling for configuring (R)(G)MII interface
The mv643xx_eth hardware has a provision for polling the PHY's
MII management registers to obtain the (R)(G)MII interface speed
(10/100/1000) and duplex (half/full) and pause (off/symmetric)
settings to use to talk to the PHY.

The driver currently does not make use of this feature.  Instead,
whenever there is a link status change event, it reads the current
link parameters from the PHY, and programs those parameters into
the mv643xx_eth MAC by hand.

This patch switches the mv643xx_eth driver to letting the MAC
auto-determine the (R)(G)MII link parameters by PHY polling, if there
is a PHY present.  For PHYless ports (when e.g. the (R)(G)MII
interface is connected to a hardware switch), we keep hardcoding the
MII interface parameters.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-07-24 06:22:59 +02:00
Saeed Bishara 5b2353859f [ARM] Kirkwood: use chip_delay
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-30 16:04:46 -04:00
Saeed Bishara 1338760329 [ARM] Kirkwood: support L2 writeback mode
This patch allows booting Kirkwood with the L2 in writeback mode,
by reading the WT override bit from the L2 config register and
passing that into the Feroceon L2 init routine, instead of assuming
that the WT override bit will always be set

Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-30 14:25:24 -04:00
Saeed Bishara 651c74c74b [ARM] add Marvell Kirkwood (88F6000) SoC support
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.

This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.

Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:06 +02:00