Commit Graph

2719 Commits

Author SHA1 Message Date
Mark Brown 56afdb70ca Merge remote-tracking branches 'spi/topic/spidev' and 'spi/topic/spidev-test' into spi-next 2015-04-11 23:09:31 +01:00
Mark Brown 165f2288e1 Merge remote-tracking branches 'spi/topic/qup', 'spi/topic/rockchip', 'spi/topic/rspi', 'spi/topic/s3c64xx' and 'spi/topic/sc18is602' into spi-next 2015-04-11 23:09:25 +01:00
Mark Brown 8afba181b9 Merge remote-tracking branches 'spi/topic/omap-100k', 'spi/topic/omap-uwire', 'spi/topic/pl022', 'spi/topic/pm' and 'spi/topic/pxa2xx' into spi-next 2015-04-11 23:09:18 +01:00
Mark Brown 35fbf8452c Merge remote-tracking branches 'spi/topic/fsl-cspi', 'spi/topic/fsl-dspi', 'spi/topic/imx' and 'spi/topic/of-id' into spi-next 2015-04-11 23:09:14 +01:00
Mark Brown 431959c079 Merge remote-tracking branches 'spi/topic/blackfin', 'spi/topic/cadence', 'spi/topic/dw' and 'spi/topic/err' into spi-next 2015-04-11 23:09:09 +01:00
Mark Brown f9de73426c Merge remote-tracking branches 'spi/topic/atmel', 'spi/topic/bcm2385', 'spi/topic/bcm2835', 'spi/topic/bcm53xx' and 'spi/topic/bitbang' into spi-next 2015-04-11 23:09:03 +01:00
Mark Brown 19655dd083 Merge remote-tracking branch 'spi/topic/img-spfi' into spi-next 2015-04-11 23:09:01 +01:00
Mark Brown e897f795a9 Merge remote-tracking branch 'spi/topic/core' into spi-next 2015-04-11 23:09:00 +01:00
Mark Brown 31d25e5cda Merge remote-tracking branches 'spi/fix/fsl-dspi', 'spi/fix/imx' and 'spi/fix/rockchip' into spi-linus 2015-04-11 23:08:56 +01:00
Mark Brown 68a595c775 Merge remote-tracking branch 'spi/fix/img-spfi' into spi-linus 2015-04-11 23:08:54 +01:00
Martin Sperl 704f32d48a spi: bcm2835: enabling polling mode for transfers shorter than 30us
In cases of short transfer times the CPU is spending lots of time
in the interrupt handler and scheduler to reschedule the worker thread.

Measurements show that we have times where it takes 29.32us to between
the last clock change and the time that the worker-thread is running again
returning from wait_for_completion_timeout().

During this time the interrupt-handler is running calling complete()
and then also the scheduler is rescheduling the worker thread.

This time can vary depending on how much of the code is still in
CPU-caches, when there is a burst of spi transfers the subsequent delays
are in the order of 25us, so the value of 30us seems reasonable.

With polling the whole transfer of 4 bytes at 10MHz finishes after 6.16us
(CS down to up) with the real transfer (clock running) taking 3.56us.
So the efficiency has much improved and is also freeing CPU cycles,
reducing interrupts and context switches.

Because of the above 30us seems to be a reasonable limit for polling.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-10 19:50:52 +01:00
Martin Sperl a30a555d74 spi: bcm2835: transform native-cs to gpio-cs on first spi_setup
Transforms the bcm-2835 native SPI-chip select to their gpio-cs equivalent.

This allows for some support of some optimizations that are not
possible due to HW-gliches on the CS line - especially filling
the FIFO before enabling SPI interrupts (by writing to CS register)
while the transfer is already in progress (See commit: e3a2be3030)

This patch also works arround some issues in bcm2835-pinctrl which does not
set the value when setting the GPIO as output - it just sets up output and
(typically) leaves the GPIO as low.  When a fix for this is merged then this
gpio_set_value can get removed from bcm2835_spi_setup.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-10 19:50:52 +01:00
Ezequiel Garcia 8c2c8c03cd spi: img-spfi: Control CS lines with GPIO
When the CONTINUE bit is set, the interrupt status we are polling to
identify if a transaction has finished can be sporadic.  Even though
the transfer has finished, the interrupt status may erroneously
indicate that there is still data in the FIFO.  This behaviour causes
random timeouts in large PIO transfers.

Instead of using the CONTINUE bit to control the CS lines, use the SPI
core's CS GPIO handling.  Also, now that the CONTINUE bit is not being
used, we can poll for the ALLDONE interrupt to indicate transfer
completion.

Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-08 21:04:51 +01:00
Mark Brown a25202b04f Merge branch 'fix/img-spfi' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-img-spfi 2015-04-08 21:04:43 +01:00
Andrew Bresticker ba33d8ac0c spi: img-spfi: Reset controller after each message
Imagination has recommended that the SPFI controller be reset after
each message, regardless of success or failure.  Do this in an
unprepare_message() callback.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-08 21:04:28 +01:00
Ezequiel Garcia 824ab37df0 spi: img-spfi: Implement a handle_err() callback
The driver can be greatly simplified by moving the transfer timeout
handling to a handle_err() callback.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-08 21:04:28 +01:00
Mark Brown 89cda06d7f Linux 4.0-rc7
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Merge tag 'v4.0-rc7' into spi-img-spfi

Linux 4.0-rc7
2015-04-08 21:04:25 +01:00
Sifan Naeem ede8342bf6 spi: img-spfi: Setup TRANSACTION register before CONTROL register
Setting the transfer length in the TRANSACTION register after the
CONTROL register is programmed causes intermittent timeout issues in
SPFI transfers when using the SPI framework to control the CS GPIO
lines.  To avoid this issue, set transfer length before programming
the CONTROL register.

Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-08 11:35:54 +01:00
Geert Uytterhoeven ff61eb4220 spi: Make master->handle_err() callback optional to avoid crashes
If a driver doesn't implement the master->handle_err() callback and an
SPI transfer fails, the kernel will crash with a NULL pointer
dereference:

    Unable to handle kernel NULL pointer dereference at virtual address 00000000
    pgd = c0003000
    [00000000] *pgd=80000040004003, *pmd=00000000
    Internal error: Oops: 80000206 [#1] SMP ARM
    Modules linked in:
    CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.0.0-rc7-koelsch-05861-g1fc9fdd4add4f783 #1046
    Hardware name: Generic R8A7791 (Flattened Device Tree)
    task: eec359c0 ti: eec54000 task.ti: eec54000
    PC is at 0x0
    LR is at spi_transfer_one_message+0x1cc/0x1f0

Make the master->handle_err() callback optional to avoid the crash.

Also fix a spelling mistake in the callback documentation while we're at
it.

Fixes: b716c4ffc6 ("spi: introduce master->handle_err() callback")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-07 19:41:32 +01:00
Andrew Bresticker 8543d0e72d spi: img-spfi: Limit bit clock to 1/4th of input clock
Although the SPFI BITCLK divider supports a value of up to 255, only
values up to 128 are usable.  This results in a maximum possible bit
clock rate of 1/4th the input clock rate.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-07 12:19:10 +01:00
Ezequiel Garcia b6fe39770a spi: img-spfi: Implement a prepare_message() callback
In preparation for switching to using the SPI core's CS GPIO handling,
move setup of the PORT_STATE register, which must be configured before
CS is asserted, to a prepare_message() callback.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-07 12:17:54 +01:00
Mark Brown 63031ed6b8 Merge branch 'fix/fsl-dspi' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-fsl-dspi
Conflicts:
	drivers/spi/spi-fsl-dspi.c
2015-04-07 11:54:40 +01:00
Aaron Brice 95bf15f386 spi: fsl-dspi: Add ~50ns delay between cs and sck
Add delay between chip select and clock signals, before clock starts and
after clock stops.

Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-06 18:12:25 +01:00
Aaron Brice e689d6df82 spi: fsl-dspi: Fix clock rate scale values
Previous algorithm had an outer loop with the values {2,3,5,7} and an
inner loop with {2,4,6,8,16,32,...,32768}, and would pick the first
value over the required scaling value (where the total scale was the two
numbers multiplied).

Since the inner loop went up to 32768 it would always pick a value of 2
for PBR and a much higher than necessary value for BR.  The desired
scale factor was being divided by two I believe to compensate for the
much higher scale factors (the divide by two not specified in the
reference manual).

Updated to check all values and find the smallest scale factor possible
without going over the desired clock rate.

Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-06 18:11:19 +01:00
Dan Carpenter c9bc3e8bf0 spi: signedness bug in qspi_trigger_transfer_out_int()
We need "ret" to be unsigned for the error handling to work.  The
signedness of "i" and "n" don't matter but qspi_set_send_trigger()
returns an int so I've changed them to int as well.

Fixes: 4b6fe3edcb ('spi: Using Trigger number to transmit/receive data')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-06 17:20:07 +01:00
Lucas Stach f511ab09df spi: imx: read back the RX/TX watermark levels earlier
They are used to decide if the controller can do DMA on a buffer
of a specific length and thus are needed before any transfer is attempted.

This fixes a memory leak where the SPI core uses the drivers can_dma()
callback to determine if a buffer needs to be mapped. As the watermark
levels aren't correct at that point the driver falsely claims to be able to
DMA the buffer when it fact it isn't.
After the transfer has been done the core uses the same callback to
determine if it needs to unmap the buffers. As the driver now correctly
claims to not being able to DMA the buffer the core doesn't attempt to
unmap the buffer which leaves the SGT leaking.

Fixes: f62caccd12 (spi: spi-imx: add DMA support)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
2015-04-01 21:32:38 +01:00
Chen Gang 057f6061a1 spi: spi-bfin5xx: Initialize cr_width in bfin_spi_pump_transfers()
cr_width may be not initialized before using by cr, the related warning
(with defconfig under blackfin by gcc5):

    CC      drivers/spi/spi-bfin5xx.o
  drivers/spi/spi-bfin5xx.c: In function 'bfin_spi_pump_transfers':
  drivers/spi/spi-bfin5xx.c:655:5: warning: 'cr_width' may be used uninitialized in this function [-Wmaybe-uninitialized]
    cr |= cr_width;
       ^

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-01 21:28:56 +01:00
Michael Grzeschik 232a5adc51 spi: bitbang: only toggle bitchanges
The current implementation of bitbang_txrx_be_cpha0 and
bitbang_txrx_be_cpha1 always call setmosi. That runs into several
unnecessary calls into the gpiolib when the level of the GPIO actually
has not to be changed.

This patch changes the routines to remember the last GPIO level
and only calls setmosi if an change has to be made. This
way it improves the transfer throughput.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-31 17:20:36 +01:00
Dan Carpenter eecacf73a4 spi: pxa2xx: missing break in pxa2xx_ssp_get_clk_div()
We refactored this code but accidentally left out a break statement so
QUARK_X1000_SSP isn't handled correctly.

Fixes: 025ffe88ee ('spi: pxa2xx: shift clk_div in one place')
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-31 15:05:43 +01:00
Aaron Brice 6fd63087d8 spi: fsl-dspi: Fix clock rate scale values
Previous algorithm had an outer loop with the values {2,3,5,7} and an
inner loop with {2,4,6,8,16,32,...,32768}, and would pick the first
value over the required scaling value (where the total scale was the two
numbers multiplied).

Since the inner loop went up to 32768 it would always pick a value of 2
for PBR and a much higher than necessary value for BR.  The desired
scale factor was being divided by two I believe to compensate for the
much higher scale factors (the divide by two not specified in the
reference manual).

Updated to check all values and find the smallest scale factor possible
without going over the desired clock rate.

Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-31 12:13:03 +01:00
Hiep Cao Minh 4b6fe3edcb spi: Using Trigger number to transmit/receive data
In order to transmit and receive data when have 32 bytes of data that
ready has prepared on Transmit/Receive Buffer to transmit or receive.
Instead transmits/receives a byte data using Transmit/Receive Buffer
Data Triggering Number will improve the speed of transfer data.

Signed-off-by: Hiep Cao Minh <cm-hiep@jinso.co.jp>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-29 21:29:35 -07:00
Martin Sperl e3a2be3030 spi: bcm2835: fill FIFO before enabling interrupts to reduce interrupts/message
To reduce the number of interrupts/message we fill the FIFO before
enabling interrupts - for short messages this reduces the interrupt count
from 2 to 1 interrupt.

There have been rare cases where short (<200ns) chip-select switches with
native CS have been observed during such operation, this is why this
optimization is only enabled for GPIO-CS.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Tested-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-29 09:53:30 -07:00
Martin Sperl 1e4df62d46 spi: bcm2835: fix code formatting issue
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Tested-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-29 09:51:53 -07:00
Mark Brown 956b200a84 spi: spidev: Warn loudly if instantiated from DT as "spidev"
Since spidev is a detail of how Linux controls a device rather than a
description of the hardware in the system we should never have a node
described as "spidev" in DT, any SPI device could be a spidev so this
is just not a useful description.

In order to help prevent users from writing such device trees generate a
warning if spidev is instantiated as a DT node without an ID in the match
table.

Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-27 16:43:03 -07:00
Martin Sperl e34ff011c7 spi: bcm2835: move to the transfer_one driver model
This also allows for GPIO-CS to get used removing the limitation of
2/3 SPI devises on the SPI bus.

Fixes: spi-cs-high with native CS with multiple devices on the spi-bus
resetting the chip selects to "normal" polarity after a finished
transfer.

No other functionality/improvements added.

Tested with the following 4 devices on the spi-bus:
* mcp2515 with native CS
* mcp2515 with gpio CS
* fb_st7735r with native CS
    (plus spi-cs-high via transistor inverting polarity)
* enc28j60 with gpio-CS
Tested-by: Martin Sperl <kernel@martin.sperl.org>

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-26 18:28:44 -07:00
Mark Brown 1be38e041f Linux 4.0-rc5
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Merge tag 'v4.0-rc5' into spi-bcm2835

Linux 4.0-rc5
2015-03-26 17:50:42 -07:00
Julius Werner 76b17e6e49 spi/rockchip: Add device tree property to configure Rx Sample Delay
We have found that we can sometimes see read failures on boards with
high-capacitance SPI lines. It seems that the controller samples the Rx
data line too early, and its register interface has an "Rx Sample Delay"
setting to fine-tune against this issue.

This patch adds a new optional device tree entry that can configure this
delay in terms of nanoseconds. The kernel will calculate the
best-fitting amount of parent clock ticks to program the controller with
based on that.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-26 17:42:21 -07:00
Julius Werner 754ec43c01 spi/rockchip: Round up clock rate divisor to err on the safe side
The Rockchip SPI driver currently calculates its clock rate divisor by
integer dividing the parent rate by the target rate, and then rounding
the result up to the next even number (since the divisor must be
even).

Clock rate divisors should always be rounded up, so that the resulting
frequency is lower or equal to the target. This is correctly done in the
second step here but not in the first, so we still have a risk of
exceeding the desired target frequency (e.g. setting spi-max-frequency
to 40000000 with a parent clock of 99000000 could lead to a divisor of
99000000 / 40000000 == 2 (which is even) that then results in an
effective frequency of 99000000 / 2 == 49500000 (potentially exceeding
the flash chip's specifications).

This patch changes the division to round up to fix this problem.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-26 17:41:52 -07:00
Dmitry Torokhov 22de3ef94b spi: of: do explicitly request modules for of-registered devices
Trying to register an SPI device asynchronously (via async_schedule() call)
results in an ugly complaint from request_module() warning about potential
deadlock (because request_module tries to wait for async works to
complete, the caller is also an async work in this case).

While we could try to switch to using request_module_nowait(), other buses,
as well as SPI itself when not using device tree, do not try to load
modules explicitly, but rather rely on the standard infrastructure (such as
udev) to execute module loading. There is no reason why SPI OF-described
devices should be treated differently.

Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-25 14:34:52 -07:00
Andy Shevchenko 207cda93f0 spi: dw: fix crash on setup stage
The commit 1a7b7ee72c (spi: Ensure that CS line is in non-active state after
spi_setup()) introduces an unconditional call of spi_set_cs() before ->setup().
The dw_spi_set_cs() relies on that fact that ->setup() is already called, but
it doesn't now. This patch fixes the crash by adding an additional check to
dw_spi_set_cs().

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-25 11:54:40 -07:00
Andy Shevchenko 9df461eca1 spi: pxa2xx: replace ugly table by approximation
The Quark SoC data sheet describes the baud rate setting using fractional
divider. The subset of possible values represented by a table suggests that the
divisor has one block that could divide by 5. This explains the number of the
beast in some cases in the table. Thus, in this particular case the divisor can
be evaluated as

	5^i * 2^j * 2 * k,

where

	i = [0, 1]
	j = [0, 23]
	k = [1, 256]

There are few cases as mentioned in the data sheet, i.e. better form of the
clock signal will be in case if DDS_CLK_RATE either 2^n or 2/5. It's also
possible to use any value that is less or equal to 0x33333 (1/5/16 = 1/80).

All three cases are compared to each other and the one that suits better is
chosen by the approximation algorithm. Anyone can play with the script [1] that
represents the algorithm.

[1] https://gist.github.com/06b084488b3629898121

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-25 08:30:17 -07:00
Mark Brown 072ac04d31 Merge remote-tracking branches 'spi/fix/dw', 'spi/fix/queue' and 'spi/fix/qup' into spi-linus 2015-03-24 10:38:44 -07:00
Andy Shevchenko 025ffe88ee spi: pxa2xx: shift clk_div in one place
This patch refactors ssp_get_clk_div() and pxa2xx_ssp_get_clk_div() to align
clk_div calculations, i.e. ssp_get_clk_div() and quark_x1000_set_clk_regvals()
will return plain clk_div and it will be shifted to proper position in
pxa2xx_ssp_get_clk_div().

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-24 09:32:48 -07:00
Ian Abbott f20fbaad76 spi: spidev: fix possible arithmetic overflow for multi-transfer message
`spidev_message()` sums the lengths of the individual SPI transfers to
determine the overall SPI message length.  It restricts the total
length, returning an error if too long, but it does not check for
arithmetic overflow.  For example, if the SPI message consisted of two
transfers and the first has a length of 10 and the second has a length
of (__u32)(-1), the total length would be seen as 9, even though the
second transfer is actually very long.  If the second transfer specifies
a null `rx_buf` and a non-null `tx_buf`, the `copy_from_user()` could
overrun the spidev's pre-allocated tx buffer before it reaches an
invalid user memory address.  Fix it by checking that neither the total
nor the individual transfer lengths exceed the maximum allowed value.

Thanks to Dan Carpenter for reporting the potential integer overflow.

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-23 14:00:51 -07:00
Martin Sperl 6935224da2 spi: bcm2835: enable support of 3-wire mode
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-23 11:54:34 -07:00
Martin Sperl 210b49231a spi: bcm2835: clock divider can be a multiple of 2
The official documentation is wrong in this respect.
Has been tested empirically for dividers 2-1024

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-23 11:52:26 -07:00
Martin Sperl 4adf312976 spi: bcm2835: fill/drain SPI-fifo as much as possible during interrupt
Implement the recommendation from the BCM2835 data-sheet
with regards to polling drivers to fill/drain the FIFO as much data as possible
also for the interrupt-driven case (which this driver is making use of).

This means that for long transfers (>64bytes) we need one interrupt
every 64 bytes instead of every 12 bytes, as the FIFO is 16 words (not bytes) wide.

Tested with mcp251x (can bus), fb_st7735 (TFT framebuffer device)
and enc28j60 (ethernet) drivers.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-23 11:48:58 -07:00
Jarkko Nikula d4f9dcd1ac spi: omap-uwire: Remove needless include asm/irq.h
asm/irq.h is already included by linux/interrupt.h.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-23 09:43:37 -07:00
Jarkko Nikula 22d1b94d4b spi: pxa2xx: Remove needless includes
These asm/io.h, asm/irq.h and asm/delay.h are needless since they are
already included by linux/io.h via drivers/spi/spi-pxa2xx.h,
linux/interrupt.h and linux/delay.h.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-23 09:43:19 -07:00
Ben Dooks ea467326e3 spi: atmel: use endian agnostic IO
Use the endian agnositc IO functions instead of the __raw ones for when
the driver is in use on big-endian systems.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-22 18:00:25 +00:00