683 lines
15 KiB
C
683 lines
15 KiB
C
#include <linux/module.h>
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#include <linux/ptrace.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <linux/nodemask.h>
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#include <linux/smp.h>
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#include <asm/apic.h>
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#include <asm/e2k_api.h>
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#include <asm/e2k.h>
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#include <asm/e2k_sic.h>
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#include <asm/sic_regs.h>
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#include <asm/sic_regs_access.h>
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#include <asm/iolinkmask.h>
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#include <asm/io.h>
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#include <asm/console.h>
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#undef DEBUG_SIC_MODE
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#undef DebugSIC
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#define DEBUG_SIC_MODE 0 /* SIC mapping & init */
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#define DebugSIC(fmt, args...) \
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({ if (DEBUG_SIC_MODE) \
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pr_debug(fmt, ##args); })
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#undef BOOT_DEBUG_SIC_MODE
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#undef BootDebugSIC
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#define BOOT_DEBUG_SIC_MODE 0 /* SIC mapping & init */
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#define BootDebugSIC(fmt, args...) \
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({ if (BOOT_DEBUG_SIC_MODE) \
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dump_printk(fmt, ##args); })
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extern int __initdata max_iolinks;
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extern int __initdata max_node_iolinks;
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int boot_get_e2k_machine_id(void)
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{
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e2k_idr_t idr;
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int mdl;
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int mach_id;
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idr = read_IDR_reg();
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mdl = idr.IDR_mdl;
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BootDebugSIC("boot_get_e2k_machine_id() CPU model is %d, "
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"IDR 0x%lx\n", mdl, idr.IDR_reg);
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if (mdl == IDR_E3S_MDL) {
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mach_id = MACHINE_ID_E3S;
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} else if (mdl == IDR_ES2_DSP_MDL) {
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mach_id = MACHINE_ID_ES2_DSP;
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} else if (mdl == IDR_ES2_RU_MDL) {
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mach_id = MACHINE_ID_ES2_RU;
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} else if (mdl == IDR_E2S_MDL) {
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mach_id = MACHINE_ID_E2S;
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} else if (mdl == IDR_E8C_MDL) {
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mach_id = MACHINE_ID_E8C;
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} else if (mdl == IDR_E1CP_MDL) {
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mach_id = MACHINE_ID_E1CP;
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} else if (mdl == IDR_E8C2_MDL) {
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mach_id = MACHINE_ID_E8C2;
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} else {
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BootDebugSIC("Undefined CPU model number %d\n", mdl);
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mach_id = MACHINE_ID_NONE;
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}
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return mach_id;
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}
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void __init
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boot_e2k_sic_setup_arch(void)
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{
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if (BOOT_HAS_MACHINE_E2K_FULL_SIC) {
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boot_machine.x86_io_area_base = E2K_FULL_SIC_IO_AREA_PHYS_BASE;
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} else if (BOOT_HAS_MACHINE_E2K_LEGACY_SIC) {
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boot_machine.x86_io_area_base =
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E2K_LEGACY_SIC_IO_AREA_PHYS_BASE;
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} else {
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pr_err("boot_e2k_sic_setup_arch() this machine has not SIC "
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"capability\n");
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}
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boot_machine.rev = read_IDR_reg().IDR_rev;
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}
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#ifdef CONFIG_PIC
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/*
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* Read IRQ # vector from PIC (implemented only on e3s and e90s)
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*/
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# define E2K_IO_APIC_PIC_IRQVEC_REG 0x0f0 /* IOAPIC register number */
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/* to read ExtINT IRQ vector */
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# define E2K_IO_APIC_AREA_PHYS_BASE 0x00000000fec00000UL
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static inline int
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io_apic_read_PIC_IRQVEC(void)
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{
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return E2K_READ_MAS_W(E2K_IO_APIC_AREA_PHYS_BASE +
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E2K_IO_APIC_PIC_IRQVEC_REG, MAS_IOADDR);
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}
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#endif
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int e2k_sic_get_vector(void)
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{
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int vector;
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vector = arch_apic_read(APIC_VECT);
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if (unlikely(APIC_VECT_IS_EXTINT(vector))) {
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#ifdef CONFIG_PIC
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/*
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* IOAPIC IRQ vector has flag of PIC IRQ/ so read now vector
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* from PIC through IOAPIC special register
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*/
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/* FIXME: IOAPICs can be more then one, but PIC can have only 1 */
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/* now we assume only BSP processor IOHUB has active PIC */
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vector = io_apic_read_PIC_IRQVEC();
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#else
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pr_emerg("Received ExtINT interrupt on kernel without PIC! "
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"Read vector is %x\n", vector);
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vector = SPURIOUS_APIC_VECTOR;
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#endif
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}
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return APIC_VECT_VECTOR(vector);
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}
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unsigned int sic_get_mc_ecc(int node, int num)
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{
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int reg_offset = 0;
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switch (num) {
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case 0:
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reg_offset = SIC_mc0_ecc;
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break;
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case 1:
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reg_offset = SIC_mc1_ecc;
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break;
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case 2:
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reg_offset = SIC_mc2_ecc;
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break;
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case 3:
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reg_offset = SIC_mc3_ecc;
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break;
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};
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if (reg_offset)
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return sic_read_node_nbsr_reg(node, reg_offset);
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return 0;
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}
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unsigned int sic_get_mc_opmb(int node, int num)
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{
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int reg_offset = 0;
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switch (num) {
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case 0:
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reg_offset = SIC_mc0_opmb;
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break;
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case 1:
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reg_offset = SIC_mc1_opmb;
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break;
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case 2:
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reg_offset = SIC_mc2_opmb;
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break;
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case 3:
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reg_offset = SIC_mc3_opmb;
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break;
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};
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if (reg_offset)
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return sic_read_node_nbsr_reg(node, reg_offset);
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return 0;
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}
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unsigned int sic_get_ipcc_csr(int node, int num)
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{
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int reg_offset = 0;
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switch (num) {
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case 1:
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reg_offset = SIC_ipcc_csr1;
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break;
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case 2:
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reg_offset = SIC_ipcc_csr2;
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break;
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case 3:
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reg_offset = SIC_ipcc_csr3;
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break;
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};
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if (reg_offset)
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return sic_read_node_nbsr_reg(node, reg_offset);
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return 0;
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}
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void sic_set_ipcc_csr(int node, int num, unsigned int reg_value)
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{
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int reg_offset = 0;
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switch (num) {
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case 1:
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reg_offset = SIC_ipcc_csr1;
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break;
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case 2:
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reg_offset = SIC_ipcc_csr2;
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break;
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case 3:
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reg_offset = SIC_ipcc_csr3;
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break;
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};
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if (reg_offset)
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sic_write_node_nbsr_reg(node, reg_offset, reg_value);
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return;
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}
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unsigned int sic_get_ipcc_pmr(int node, int num)
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{
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int reg_offset = 0;
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switch (num) {
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case 1:
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reg_offset = SIC_ipcc_pmr1;
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break;
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case 2:
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reg_offset = SIC_ipcc_pmr2;
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break;
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case 3:
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reg_offset = SIC_ipcc_pmr3;
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break;
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};
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if (reg_offset)
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return sic_read_node_nbsr_reg(node, reg_offset);
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return 0;
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}
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unsigned int sic_get_ipcc_str(int node, int num)
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{
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int reg_offset = 0;
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switch (num) {
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case 1:
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reg_offset = SIC_ipcc_str1;
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break;
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case 2:
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reg_offset = SIC_ipcc_str2;
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break;
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case 3:
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reg_offset = SIC_ipcc_str3;
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break;
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};
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if (reg_offset)
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return sic_read_node_nbsr_reg(node, reg_offset);
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return 0;
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}
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void sic_set_ipcc_str(int node, int num, unsigned int val)
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{
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int reg_offset = 0;
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switch (num) {
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case 1:
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reg_offset = SIC_ipcc_str1;
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break;
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case 2:
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reg_offset = SIC_ipcc_str2;
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break;
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case 3:
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reg_offset = SIC_ipcc_str3;
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break;
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};
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if (reg_offset)
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sic_write_node_nbsr_reg(node, reg_offset, val);
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}
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unsigned int sic_get_io_csr(int node, int num)
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{
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int reg_offset = 0;
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switch (num) {
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case 0:
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reg_offset = SIC_io_csr;
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break;
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case 1:
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reg_offset = ((IS_MACHINE_ES2) ? SIC_io_csr1 : SIC_io_csr_hi);
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break;
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};
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if (reg_offset)
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return sic_read_node_nbsr_reg(node, reg_offset);
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return 0;
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}
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unsigned int sic_get_io_tmr(int node, int num)
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{
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int reg_offset = 0;
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switch (num) {
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case 0:
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reg_offset = SIC_io_tmr;
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break;
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case 1:
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reg_offset = ((IS_MACHINE_ES2) ? SIC_io_tmr1 : SIC_io_tmr_hi);
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break;
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};
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if (reg_offset)
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return sic_read_node_nbsr_reg(node, reg_offset);
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return 0;
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}
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unsigned int sic_get_io_str(int node, int num)
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{
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int reg_offset = 0;
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switch (num) {
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case 0:
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reg_offset = SIC_io_str;
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break;
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case 1:
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reg_offset = ((IS_MACHINE_ES2) ? SIC_io_str1 : SIC_io_str_hi);
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break;
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};
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if (reg_offset)
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return sic_read_node_nbsr_reg(node, reg_offset);
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return 0;
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}
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void sic_set_io_str(int node, int num, unsigned int val)
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{
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int reg_offset = 0;
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switch (num) {
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case 0:
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reg_offset = SIC_io_str;
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break;
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case 1:
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reg_offset = ((IS_MACHINE_ES2) ? SIC_io_str1 : SIC_io_str_hi);
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break;
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};
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if (reg_offset)
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sic_write_node_nbsr_reg(node, reg_offset, val);
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}
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unsigned int sic_get_pl_csr(int node, int num)
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{
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int reg_offset = 0;
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switch (num) {
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case 0:
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reg_offset = SIC_pl_csr1;
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break;
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case 1:
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reg_offset = SIC_pl_csr2;
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break;
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case 2:
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reg_offset = SIC_pl_csr3;
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break;
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};
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if (reg_offset)
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return sic_read_node_nbsr_reg(node, reg_offset);
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return 0;
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}
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static void create_nodes_io_config(void);
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int __init
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e2k_early_iohub_online(int node, int link)
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{
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e2k_iol_csr_struct_t io_link;
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e2k_io_csr_struct_t io_hub;
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int domain = node_iolink_to_domain(node, link);
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int iohub_on = 0;
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DebugENBSR("started on node %d link %d\n",
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node, link);
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if (!node_online(node))
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return 0;
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if (domain >= max_iolinks)
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return 0;
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if (link >= max_node_iolinks)
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return 0;
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/* FIXME: IO link registers of SIC mutate to WLCC registers */
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/* on legacy SIC */
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/* now we assume IO link on node #0 connected to IOHUB online */
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if (HAS_MACHINE_E2K_LEGACY_SIC) {
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iohub_on = 1;
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} else {
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io_link.E2K_IOL_CSR_reg = early_sic_read_node_iolink_nbsr_reg(
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node, link, SIC_iol_csr);
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if (io_link.E2K_IOL_CSR_mode != IOHUB_IOL_MODE)
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return 0;
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io_hub.E2K_IO_CSR_reg = early_sic_read_node_iolink_nbsr_reg(
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node, link, SIC_io_csr);
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if (io_hub.E2K_IO_CSR_ch_on) {
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iohub_on = 1;
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}
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}
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DebugENBSR("IOHUB of node %d link %d %s\n",
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node, link, (iohub_on) ? "ON" : "OFF");
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return iohub_on;
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}
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/*
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* SIC area mapping and init
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*/
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unsigned char *nodes_nbsr_base[MAX_NUMNODES] = { NULL };
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EXPORT_SYMBOL(nodes_nbsr_base);
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int __init
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e2k_sic_init(void)
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{
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unsigned char *nbsr_base;
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unsigned long long phys_base;
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int node;
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int ret = 0;
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if (!HAS_MACHINE_L_SIC) {
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printk("e2k_sic_init() the arch has not SIC\n");
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return -ENODEV;
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}
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for_each_online_node(node) {
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phys_base = (unsigned long long)THE_NODE_NBSR_PHYS_BASE(node);
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nbsr_base = ioremap(phys_base, NODE_NBSR_SIZE);
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if (nbsr_base == NULL) {
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printk("e2k_sic_init() could not map NBSR registers "
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"of node #%d, phys base 0x%llx, size 0x%lx\n",
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node, phys_base, NODE_NBSR_SIZE);
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ret =-ENOMEM;
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}
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DebugSIC("map NBSR of node #%d phys base "
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"0x%llx, size 0x%lx to virtual addr 0x%p\n",
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node, phys_base, NODE_NBSR_SIZE, nbsr_base);
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nodes_nbsr_base[node] = nbsr_base;
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}
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create_nodes_io_config();
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return ret;
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}
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unsigned long domain_to_pci_conf_base[MAX_NUMIOLINKS] = {
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[ 0 ... (MAX_NUMIOLINKS-1) ] = 0
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};
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#ifdef CONFIG_IOHUB_DOMAINS
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static void create_nodes_pci_conf(void)
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{
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int domain;
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for_each_iohub(domain) {
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domain_to_pci_conf_base[domain] =
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sic_domain_pci_conf_base(domain);
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DebugSIC("IOHUB domain #%d (node %d, "
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"IO link %d) PCI CFG base 0x%lx\n",
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domain, iohub_domain_to_node(domain),
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iohub_domain_to_link(domain),
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domain_to_pci_conf_base[domain]);
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}
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}
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#else /* !CONFIG_IOHUB_DOMAINS: */
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static void create_nodes_pci_conf(void)
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{
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domain_to_pci_conf_base[0] =
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sic_domain_pci_conf_base(0);
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}
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#endif /* !CONFIG_IOHUB_DOMAINS */
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#ifdef CONFIG_IOHUB_DOMAINS
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/*
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* IO Links of all nodes configuration
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*/
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static void create_iolink_config(int node, int link)
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{
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e2k_iol_csr_struct_t io_link;
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e2k_io_csr_struct_t io_hub;
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e2k_rdma_cs_struct_t rdma;
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int link_on;
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link_on = 0;
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/* FIXME: IO link registers of SIC mutate to WLCC registers */
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/* on legacy SIC */
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/* now we assume IO link on node #0 connected to IOHUB online */
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if (HAS_MACHINE_E2K_LEGACY_SIC) {
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io_link.E2K_IOL_CSR_reg = 0;
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io_link.E2K_IOL_CSR_mode = IOHUB_IOL_MODE;
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io_link.E2K_IOL_CSR_abtype = IOHUB_ONLY_IOL_ABTYPE;
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} else {
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io_link.E2K_IOL_CSR_reg = sic_read_node_iolink_nbsr_reg(
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node, link, SIC_iol_csr);
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}
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printk(KERN_INFO "Node #%d IO LINK #%d is", node, link);
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if (io_link.E2K_IOL_CSR_mode == IOHUB_IOL_MODE) {
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node_iohub_set(node, link, iolink_iohub_map);
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iolink_iohub_num ++;
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printk(" IO HUB controller");
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/* FIXME: IO link registers of SIC mutate to WLCC registers */
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/* on legacy SIC */
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/* now we assume IO link on node #0 connected to IOHUB online */
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if (HAS_MACHINE_E2K_LEGACY_SIC) {
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io_hub.E2K_IO_CSR_reg = 0;
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io_hub.E2K_IO_CSR_ch_on = 1;
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} else {
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io_hub.E2K_IO_CSR_reg = sic_read_node_iolink_nbsr_reg(
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node, link, SIC_io_csr);
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}
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if (io_hub.E2K_IO_CSR_ch_on) {
|
|
node_iohub_set(node, link, iolink_online_iohub_map);
|
|
iolink_online_iohub_num ++;
|
|
link_on = 1;
|
|
printk(" ON");
|
|
} else {
|
|
printk(" OFF");
|
|
}
|
|
} else {
|
|
node_rdma_set(node, link, iolink_rdma_map);
|
|
iolink_rdma_num ++;
|
|
printk(" RDMA controller");
|
|
rdma.E2K_RDMA_CS_reg =
|
|
sic_read_node_iolink_nbsr_reg(node, link, SIC_rdma_cs);
|
|
if (rdma.E2K_RDMA_CS_ch_on) {
|
|
node_rdma_set(node, link, iolink_online_rdma_map);
|
|
iolink_online_rdma_num ++;
|
|
link_on = 1;
|
|
printk(" ON 0x%08x", rdma.E2K_RDMA_CS_reg);
|
|
} else {
|
|
printk(" OFF 0x%08x", rdma.E2K_RDMA_CS_reg);
|
|
}
|
|
}
|
|
if (link_on) {
|
|
int ab_type = io_link.E2K_IOL_CSR_abtype;
|
|
printk(" connected to");
|
|
switch (ab_type) {
|
|
case IOHUB_ONLY_IOL_ABTYPE:
|
|
printk(" IO HUB controller");
|
|
break;
|
|
case RDMA_ONLY_IOL_ABTYPE:
|
|
printk(" RDMA controller");
|
|
break;
|
|
case RDMA_IOHUB_IOL_ABTYPE:
|
|
printk(" IO HUB/RDMA controller");
|
|
break;
|
|
default:
|
|
printk(" unknown controller");
|
|
break;
|
|
}
|
|
}
|
|
printk("\n");
|
|
}
|
|
|
|
static void __init create_nodes_io_config(void)
|
|
{
|
|
int node;
|
|
int link;
|
|
|
|
for_each_online_node(node) {
|
|
for_each_iolink_of_node(link) {
|
|
if (iolinks_num >= max_iolinks)
|
|
break;
|
|
if (link >= max_node_iolinks)
|
|
break;
|
|
iolinks_num ++;
|
|
create_iolink_config(node, link);
|
|
}
|
|
if (iolinks_num >= max_iolinks)
|
|
break;
|
|
}
|
|
if (iolinks_num > 1) {
|
|
printk(KERN_INFO "Total IO links %d: IOHUBs %d, RDMAs %d\n",
|
|
iolinks_num, iolink_iohub_num, iolink_rdma_num);
|
|
}
|
|
create_nodes_pci_conf();
|
|
}
|
|
#else /* !CONFIG_IOHUB_DOMAINS */
|
|
|
|
/*
|
|
* IO Link of nodes configuration
|
|
*/
|
|
nodemask_t node_iohub_map = NODE_MASK_NONE;
|
|
nodemask_t node_online_iohub_map = NODE_MASK_NONE;
|
|
int node_iohub_num = 0;
|
|
int node_online_iohub_num = 0;
|
|
nodemask_t node_rdma_map = NODE_MASK_NONE;
|
|
nodemask_t node_online_rdma_map = NODE_MASK_NONE;
|
|
int node_rdma_num = 0;
|
|
int node_online_rdma_num = 0;
|
|
|
|
static void __init create_nodes_io_config(void)
|
|
{
|
|
int node;
|
|
e2k_iol_csr_struct_t io_link;
|
|
e2k_io_csr_struct_t io_hub;
|
|
e2k_rdma_cs_struct_t rdma;
|
|
int link_on;
|
|
|
|
for_each_online_node(node) {
|
|
link_on = 0;
|
|
/* FIXME: IO link registers of SIC mutate to WLCC registers */
|
|
/* on legacy SIC */
|
|
/* now we assume IO link on node #0 connected to IOHUB online */
|
|
if (HAS_MACHINE_E2K_LEGACY_SIC) {
|
|
io_link.E2K_IOL_CSR_reg = 0;
|
|
io_link.E2K_IOL_CSR_mode = IOHUB_IOL_MODE;
|
|
io_link.E2K_IOL_CSR_abtype = IOHUB_ONLY_IOL_ABTYPE;
|
|
} else {
|
|
io_link.E2K_IOL_CSR_reg = sic_read_node_nbsr_reg(node,
|
|
SIC_iol_csr);
|
|
}
|
|
printk("Node #%d IO LINK is", node);
|
|
if (io_link.E2K_IOL_CSR_mode == IOHUB_IOL_MODE) {
|
|
node_set(node, node_iohub_map);
|
|
node_iohub_num ++;
|
|
printk(" IO HUB controller");
|
|
/* FIXME: IO link registers of SIC mutate to WLCC */
|
|
/* registers on legacy SIC */
|
|
/* now we assume IO link on node #0 connected to */
|
|
/* IOHUB online */
|
|
if (HAS_MACHINE_E2K_LEGACY_SIC) {
|
|
io_hub.E2K_IO_CSR_reg = 0;
|
|
io_hub.E2K_IO_CSR_ch_on = 1;
|
|
} else {
|
|
io_hub.E2K_IO_CSR_reg =
|
|
sic_read_node_nbsr_reg(node,
|
|
SIC_io_csr);
|
|
}
|
|
if (io_hub.E2K_IO_CSR_ch_on) {
|
|
node_set(node, node_online_iohub_map);
|
|
node_online_iohub_num ++;
|
|
link_on = 1;
|
|
printk(" ON");
|
|
} else {
|
|
printk(" OFF");
|
|
}
|
|
} else {
|
|
node_set(node, node_rdma_map);
|
|
node_rdma_num ++;
|
|
printk(" RDMA controller");
|
|
rdma.E2K_RDMA_CS_reg =
|
|
sic_read_node_nbsr_reg(node, SIC_rdma_cs);
|
|
if (rdma.E2K_RDMA_CS_ch_on) {
|
|
node_set(node, node_online_rdma_map);
|
|
node_online_rdma_num ++;
|
|
link_on = 1;
|
|
printk(" ON 0x%08x", rdma.E2K_RDMA_CS_reg);
|
|
} else {
|
|
printk(" OFF 0x%08x", rdma.E2K_RDMA_CS_reg);
|
|
}
|
|
}
|
|
if (link_on) {
|
|
int ab_type = io_link.E2K_IOL_CSR_abtype;
|
|
printk(" connected to");
|
|
switch (ab_type) {
|
|
case IOHUB_ONLY_IOL_ABTYPE:
|
|
printk(" IO HUB controller");
|
|
break;
|
|
case RDMA_ONLY_IOL_ABTYPE:
|
|
printk(" RDMA controller");
|
|
break;
|
|
case RDMA_IOHUB_IOL_ABTYPE:
|
|
printk(" IO HUB/RDMA controller");
|
|
break;
|
|
default:
|
|
printk(" unknown controller");
|
|
break;
|
|
}
|
|
}
|
|
printk("\n");
|
|
}
|
|
create_nodes_pci_conf();
|
|
}
|
|
/* Add for rdma_sic module */
|
|
EXPORT_SYMBOL(node_rdma_num);
|
|
EXPORT_SYMBOL(node_online_rdma_map);
|
|
EXPORT_SYMBOL(node_online_rdma_num);
|
|
|
|
#endif /* !CONFIG_IOHUB_DOMAINS */
|