121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
/*
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* LMS simulator's hardware implementation dependant procedures.
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*/
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#include <asm/apic.h>
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#include <asm/e2k_api.h>
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#include <asm/e2k.h>
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#include <asm/lms.h>
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#include <asm/e3m.h>
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#include <asm/iolinkmask.h>
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#include <asm/machdep.h>
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#include <asm/mas.h>
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#include <asm/boot_head.h>
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#include <asm/io.h>
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#include <asm/console.h>
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void __init
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boot_e3m_lms_setup_arch(void)
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{
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boot_machine.x86_io_area_base = E3M_X86_IO_AREA_PHYS_BASE;
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boot_machine.rev = E3M_LMS_CPU_REVISION;
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boot_machine.iset_ver = ELBRUS_ISET;
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}
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static void
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e3m_lms_setup_cpu_info(cpuinfo_e2k_t *cpu_info)
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{
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strncpy(cpu_info->vendor, E3M_LMS_CPU_VENDOR, 16);
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cpu_info->family = E3M_LMS_CPU_FAMILY;
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cpu_info->model = E3M_LMS_CPU_MODEL;
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cpu_info->revision = E3M_LMS_CPU_REVISION;
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cpu_info->L1_size = E3M_LMS_L1_CACHE_SIZE;
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cpu_info->L1_bytes = E3M_LMS_L1_CACHE_BYTES;
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cpu_info->L2_size = E3M_LMS_L2_CACHE_SIZE;
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cpu_info->L2_bytes = E3M_LMS_L2_CACHE_BYTES;
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}
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/*
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* If kernel was loaded by binary compilator (flash image on lms)
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* it set protection bits in North Bridge
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* Clear all protection bits in IO chip
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*/
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#define E3M_BINCO_PROT_R0 0xfff8000000UL
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#define E3M_BINCO_PROT_R1 0xfff8000004UL
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#define E3M_BINCO_PROT_R2 0xfff8000008UL
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#define E3M_BINCO_PROT_R3 0xfff800000cUL
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#define E3M_BINCO_PROT_R4 0xfff8000010UL
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#define E3M_BINCO_PROT_R5 0xfff8000014UL
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#define E3M_BINCO_PROT_R6 0xfff8000018UL
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#define E3M_BINCO_PROT_R7 0xfff800001cUL
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extern void inline
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e3m_lms_clear_binco_prot(void)
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{
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/* Clear all binary compiler protection maps */
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E2K_WRITE_MAS_W(E3M_BINCO_PROT_R0, 0, MAS_IOADDR);
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E2K_WRITE_MAS_W(E3M_BINCO_PROT_R1, 0, MAS_IOADDR);
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E2K_WRITE_MAS_W(E3M_BINCO_PROT_R2, 0, MAS_IOADDR);
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E2K_WRITE_MAS_W(E3M_BINCO_PROT_R3, 0, MAS_IOADDR);
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E2K_WRITE_MAS_W(E3M_BINCO_PROT_R4, 0, MAS_IOADDR);
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E2K_WRITE_MAS_W(E3M_BINCO_PROT_R5, 0, MAS_IOADDR);
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E2K_WRITE_MAS_W(E3M_BINCO_PROT_R6, 0, MAS_IOADDR);
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E2K_WRITE_MAS_W(E3M_BINCO_PROT_R7, 0, MAS_IOADDR);
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}
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static void
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e3m_reset_machine(void)
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{
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outb(6, 0xcf9);
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}
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static void
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e3m_halt_machine(void)
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{
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printk("Hardware support to power off is not until supported by "
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"kernel, so use manual mode\n");
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}
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#ifdef CONFIG_IOHUB_DOMAINS
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/*
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* This e3m machine has not IO link and is connect to PIIX4 controller
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* through North breadge, so it has only one IO bus and PCI domain # 0
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*/
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void __init
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e3m_lms_create_io_config(void)
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{
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char src_buffer[80];
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char *buffer = src_buffer;
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iolinks_num = 1;
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iohub_set(0, iolink_iohub_map);
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iohub_set(0, iolink_online_iohub_map);
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iolink_iohub_num = 1;
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iolink_online_iohub_num = 1;
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buffer += iolinkmask_scnprintf(buffer, 80, iolink_online_iohub_map);
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buffer[0] = '\0';
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}
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#endif /* CONFIG_IOHUB_DOMAINS */
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void __init
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e3m_lms_setup_arch(void)
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{
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int nid;
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e2k_setup_arch();
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for_each_node_has_dup_kernel(nid) {
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the_node_machine(nid)->iset = NULL;
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the_node_machine(nid)->setup_arch = e3m_lms_setup_arch;
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the_node_machine(nid)->setup_cpu_info =
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e3m_lms_setup_cpu_info;
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the_node_machine(nid)->arch_reset = e3m_reset_machine;
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the_node_machine(nid)->arch_halt = e3m_halt_machine;
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the_node_machine(nid)->get_irq_vector = e3m_get_vector;
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}
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#ifdef CONFIG_IOHUB_DOMAINS
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e3m_lms_create_io_config();
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#endif /* CONFIG_IOHUB_DOMAINS */
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e3m_lms_clear_binco_prot();
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}
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