Joseph Lo 0017f447cc clk: tegra114: add LP1 suspend/resume support ... When the system suspends to LP1, the CPU clock source is switched to CLK_M (12MHz Oscillator) during suspend/resume flow. The CPU clock source is controlled by the CCLKG_BURST_POLICY register, and hence this register must be restored during LP1 resume. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>		2013-08-12 12:22:39 -06:00
..
clk-audio-sync.c	clk: tegra: add Tegra specific clocks	2013-01-28 11:19:07 -07:00
clk-divider.c	clk: tegra: add Tegra specific clocks	2013-01-28 11:19:07 -07:00
clk-periph-gate.c	clk: tegra: Workaround for Tegra114 MSENC problem	2013-04-04 16:10:59 -06:00
clk-periph.c	clk: tegra: Add flags to tegra_clk_periph()	2013-04-04 16:10:56 -06:00
clk-pll-out.c	clk: tegra: add Tegra specific clocks	2013-01-28 11:19:07 -07:00
clk-pll.c	clk: tegra: Use override bits when needed	2013-06-11 18:00:32 -07:00
clk-super.c	clk: tegra: Implement locking for super clock	2013-02-12 10:29:12 -07:00
clk-tegra20.c	clk: tegra: Use common of_clk_init function	2013-05-31 12:57:25 -07:00
clk-tegra30.c	The common clock framework changes for 3.11 include new clock drivers	2013-07-03 11:54:50 -07:00
clk-tegra114.c	clk: tegra114: add LP1 suspend/resume support	2013-08-12 12:22:39 -06:00
clk.c	clk: tegra: Use common of_clk_init function	2013-05-31 12:57:25 -07:00
clk.h	clk: tegra: T114: add DFLL DVCO reset control	2013-06-18 11:28:51 -07:00
Makefile	clk: tegra: Implement clocks for Tegra114	2013-04-04 17:17:12 -06:00