Maxime Ripard 59f0ec231f clk: sunxi: pll2: Fix clock running too fast ... Contrary to what the datasheet says, the pre divider doesn't seem to be incremented by one in the PLL2, but just uses the value from the register, with 0 being a bypass. This fixes the audio playing too fast. Since we now have the same pre-divider flags, and the only difference with the A10 is the post-divider offset, also remove the structure to just pass the offset as an argument. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Fixes: eb662f8547 ("clk: sunxi: pll2: Add A13 support") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2015-12-02 23:27:47 -08:00
..
clk-a10-codec.c	clk: sunxi: codec clock support	2015-10-21 21:51:28 +02:00
clk-a10-hosc.c
clk-a10-mod1.c	clk: sunxi: mod1 clock support	2015-10-21 21:51:29 +02:00
clk-a10-pll2.c	clk: sunxi: pll2: Fix clock running too fast	2015-12-02 23:27:47 -08:00
clk-a20-gmac.c
clk-factors.c
clk-factors.h
clk-mod0.c
clk-simple-gates.c
clk-sun6i-apb0-gates.c
clk-sun6i-apb0.c
clk-sun6i-ar100.c
clk-sun8i-apb0.c
clk-sun8i-mbus.c
clk-sun9i-core.c
clk-sun9i-mmc.c
clk-sunxi.c
clk-usb.c
Makefile	clk: sunxi: mod1 clock support	2015-10-21 21:51:29 +02:00