827 lines
20 KiB
C
827 lines
20 KiB
C
/*
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* Performance counter support - powerpc architecture code
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*
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/perf_counter.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <asm/reg.h>
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#include <asm/pmc.h>
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#include <asm/machdep.h>
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#include <asm/firmware.h>
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struct cpu_hw_counters {
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int n_counters;
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int n_percpu;
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int disabled;
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int n_added;
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struct perf_counter *counter[MAX_HWCOUNTERS];
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unsigned int events[MAX_HWCOUNTERS];
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u64 mmcr[3];
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u8 pmcs_enabled;
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};
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DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
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struct power_pmu *ppmu;
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/*
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* Normally, to ignore kernel events we set the FCS (freeze counters
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* in supervisor mode) bit in MMCR0, but if the kernel runs with the
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* hypervisor bit set in the MSR, or if we are running on a processor
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* where the hypervisor bit is forced to 1 (as on Apple G5 processors),
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* then we need to use the FCHV bit to ignore kernel events.
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*/
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static unsigned int freeze_counters_kernel = MMCR0_FCS;
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void perf_counter_print_debug(void)
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{
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}
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/*
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* Read one performance monitor counter (PMC).
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*/
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static unsigned long read_pmc(int idx)
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{
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unsigned long val;
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switch (idx) {
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case 1:
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val = mfspr(SPRN_PMC1);
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break;
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case 2:
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val = mfspr(SPRN_PMC2);
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break;
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case 3:
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val = mfspr(SPRN_PMC3);
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break;
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case 4:
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val = mfspr(SPRN_PMC4);
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break;
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case 5:
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val = mfspr(SPRN_PMC5);
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break;
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case 6:
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val = mfspr(SPRN_PMC6);
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break;
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case 7:
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val = mfspr(SPRN_PMC7);
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break;
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case 8:
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val = mfspr(SPRN_PMC8);
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break;
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default:
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printk(KERN_ERR "oops trying to read PMC%d\n", idx);
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val = 0;
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}
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return val;
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}
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/*
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* Write one PMC.
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*/
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static void write_pmc(int idx, unsigned long val)
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{
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switch (idx) {
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case 1:
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mtspr(SPRN_PMC1, val);
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break;
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case 2:
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mtspr(SPRN_PMC2, val);
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break;
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case 3:
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mtspr(SPRN_PMC3, val);
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break;
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case 4:
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mtspr(SPRN_PMC4, val);
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break;
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case 5:
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mtspr(SPRN_PMC5, val);
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break;
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case 6:
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mtspr(SPRN_PMC6, val);
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break;
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case 7:
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mtspr(SPRN_PMC7, val);
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break;
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case 8:
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mtspr(SPRN_PMC8, val);
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break;
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default:
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printk(KERN_ERR "oops trying to write PMC%d\n", idx);
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}
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}
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/*
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* Check if a set of events can all go on the PMU at once.
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* If they can't, this will look at alternative codes for the events
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* and see if any combination of alternative codes is feasible.
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* The feasible set is returned in event[].
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*/
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static int power_check_constraints(unsigned int event[], int n_ev)
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{
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u64 mask, value, nv;
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unsigned int alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
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u64 amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
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u64 avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
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u64 smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];
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int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];
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int i, j;
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u64 addf = ppmu->add_fields;
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u64 tadd = ppmu->test_adder;
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if (n_ev > ppmu->n_counter)
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return -1;
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/* First see if the events will go on as-is */
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for (i = 0; i < n_ev; ++i) {
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alternatives[i][0] = event[i];
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if (ppmu->get_constraint(event[i], &amasks[i][0],
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&avalues[i][0]))
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return -1;
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choice[i] = 0;
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}
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value = mask = 0;
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for (i = 0; i < n_ev; ++i) {
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nv = (value | avalues[i][0]) + (value & avalues[i][0] & addf);
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if ((((nv + tadd) ^ value) & mask) != 0 ||
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(((nv + tadd) ^ avalues[i][0]) & amasks[i][0]) != 0)
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break;
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value = nv;
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mask |= amasks[i][0];
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}
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if (i == n_ev)
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return 0; /* all OK */
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/* doesn't work, gather alternatives... */
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if (!ppmu->get_alternatives)
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return -1;
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for (i = 0; i < n_ev; ++i) {
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n_alt[i] = ppmu->get_alternatives(event[i], alternatives[i]);
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for (j = 1; j < n_alt[i]; ++j)
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ppmu->get_constraint(alternatives[i][j],
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&amasks[i][j], &avalues[i][j]);
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}
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/* enumerate all possibilities and see if any will work */
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i = 0;
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j = -1;
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value = mask = nv = 0;
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while (i < n_ev) {
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if (j >= 0) {
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/* we're backtracking, restore context */
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value = svalues[i];
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mask = smasks[i];
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j = choice[i];
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}
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/*
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* See if any alternative k for event i,
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* where k > j, will satisfy the constraints.
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*/
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while (++j < n_alt[i]) {
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nv = (value | avalues[i][j]) +
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(value & avalues[i][j] & addf);
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if ((((nv + tadd) ^ value) & mask) == 0 &&
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(((nv + tadd) ^ avalues[i][j])
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& amasks[i][j]) == 0)
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break;
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}
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if (j >= n_alt[i]) {
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/*
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* No feasible alternative, backtrack
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* to event i-1 and continue enumerating its
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* alternatives from where we got up to.
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*/
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if (--i < 0)
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return -1;
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} else {
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/*
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* Found a feasible alternative for event i,
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* remember where we got up to with this event,
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* go on to the next event, and start with
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* the first alternative for it.
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*/
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choice[i] = j;
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svalues[i] = value;
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smasks[i] = mask;
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value = nv;
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mask |= amasks[i][j];
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++i;
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j = -1;
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}
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}
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/* OK, we have a feasible combination, tell the caller the solution */
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for (i = 0; i < n_ev; ++i)
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event[i] = alternatives[i][choice[i]];
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return 0;
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}
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/*
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* Check if newly-added counters have consistent settings for
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* exclude_{user,kernel,hv} with each other and any previously
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* added counters.
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*/
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static int check_excludes(struct perf_counter **ctrs, int n_prev, int n_new)
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{
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int eu, ek, eh;
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int i, n;
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struct perf_counter *counter;
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n = n_prev + n_new;
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if (n <= 1)
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return 0;
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eu = ctrs[0]->hw_event.exclude_user;
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ek = ctrs[0]->hw_event.exclude_kernel;
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eh = ctrs[0]->hw_event.exclude_hv;
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if (n_prev == 0)
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n_prev = 1;
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for (i = n_prev; i < n; ++i) {
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counter = ctrs[i];
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if (counter->hw_event.exclude_user != eu ||
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counter->hw_event.exclude_kernel != ek ||
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counter->hw_event.exclude_hv != eh)
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return -EAGAIN;
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}
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return 0;
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}
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static void power_perf_read(struct perf_counter *counter)
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{
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long val, delta, prev;
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if (!counter->hw.idx)
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return;
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/*
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* Performance monitor interrupts come even when interrupts
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* are soft-disabled, as long as interrupts are hard-enabled.
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* Therefore we treat them like NMIs.
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*/
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do {
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prev = atomic64_read(&counter->hw.prev_count);
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barrier();
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val = read_pmc(counter->hw.idx);
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} while (atomic64_cmpxchg(&counter->hw.prev_count, prev, val) != prev);
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/* The counters are only 32 bits wide */
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delta = (val - prev) & 0xfffffffful;
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atomic64_add(delta, &counter->count);
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atomic64_sub(delta, &counter->hw.period_left);
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}
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/*
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* Disable all counters to prevent PMU interrupts and to allow
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* counters to be added or removed.
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*/
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u64 hw_perf_save_disable(void)
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{
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struct cpu_hw_counters *cpuhw;
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unsigned long ret;
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unsigned long flags;
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local_irq_save(flags);
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cpuhw = &__get_cpu_var(cpu_hw_counters);
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ret = cpuhw->disabled;
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if (!ret) {
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cpuhw->disabled = 1;
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cpuhw->n_added = 0;
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/*
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* Check if we ever enabled the PMU on this cpu.
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*/
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if (!cpuhw->pmcs_enabled) {
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if (ppc_md.enable_pmcs)
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ppc_md.enable_pmcs();
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cpuhw->pmcs_enabled = 1;
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}
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/*
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* Set the 'freeze counters' bit.
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* The barrier is to make sure the mtspr has been
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* executed and the PMU has frozen the counters
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* before we return.
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*/
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mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) | MMCR0_FC);
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mb();
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}
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local_irq_restore(flags);
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return ret;
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}
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/*
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* Re-enable all counters if disable == 0.
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* If we were previously disabled and counters were added, then
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* put the new config on the PMU.
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*/
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void hw_perf_restore(u64 disable)
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{
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struct perf_counter *counter;
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struct cpu_hw_counters *cpuhw;
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unsigned long flags;
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long i;
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unsigned long val;
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s64 left;
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unsigned int hwc_index[MAX_HWCOUNTERS];
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if (disable)
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return;
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local_irq_save(flags);
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cpuhw = &__get_cpu_var(cpu_hw_counters);
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cpuhw->disabled = 0;
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/*
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* If we didn't change anything, or only removed counters,
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* no need to recalculate MMCR* settings and reset the PMCs.
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* Just reenable the PMU with the current MMCR* settings
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* (possibly updated for removal of counters).
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*/
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if (!cpuhw->n_added) {
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mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
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mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
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mtspr(SPRN_MMCR0, cpuhw->mmcr[0]);
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if (cpuhw->n_counters == 0)
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get_lppaca()->pmcregs_in_use = 0;
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goto out;
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}
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/*
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* Compute MMCR* values for the new set of counters
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*/
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if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_counters, hwc_index,
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cpuhw->mmcr)) {
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/* shouldn't ever get here */
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printk(KERN_ERR "oops compute_mmcr failed\n");
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goto out;
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}
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/*
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* Add in MMCR0 freeze bits corresponding to the
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* hw_event.exclude_* bits for the first counter.
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* We have already checked that all counters have the
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* same values for these bits as the first counter.
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*/
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counter = cpuhw->counter[0];
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if (counter->hw_event.exclude_user)
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cpuhw->mmcr[0] |= MMCR0_FCP;
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if (counter->hw_event.exclude_kernel)
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cpuhw->mmcr[0] |= freeze_counters_kernel;
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if (counter->hw_event.exclude_hv)
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cpuhw->mmcr[0] |= MMCR0_FCHV;
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/*
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* Write the new configuration to MMCR* with the freeze
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* bit set and set the hardware counters to their initial values.
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* Then unfreeze the counters.
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*/
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get_lppaca()->pmcregs_in_use = 1;
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mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
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mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
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mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
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| MMCR0_FC);
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/*
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* Read off any pre-existing counters that need to move
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* to another PMC.
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*/
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for (i = 0; i < cpuhw->n_counters; ++i) {
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counter = cpuhw->counter[i];
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if (counter->hw.idx && counter->hw.idx != hwc_index[i] + 1) {
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power_perf_read(counter);
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write_pmc(counter->hw.idx, 0);
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counter->hw.idx = 0;
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}
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}
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/*
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* Initialize the PMCs for all the new and moved counters.
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*/
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for (i = 0; i < cpuhw->n_counters; ++i) {
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counter = cpuhw->counter[i];
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if (counter->hw.idx)
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continue;
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val = 0;
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if (counter->hw_event.irq_period) {
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left = atomic64_read(&counter->hw.period_left);
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if (left < 0x80000000L)
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val = 0x80000000L - left;
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}
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atomic64_set(&counter->hw.prev_count, val);
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counter->hw.idx = hwc_index[i] + 1;
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write_pmc(counter->hw.idx, val);
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}
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mb();
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cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
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mtspr(SPRN_MMCR0, cpuhw->mmcr[0]);
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out:
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local_irq_restore(flags);
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}
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static int collect_events(struct perf_counter *group, int max_count,
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struct perf_counter *ctrs[], unsigned int *events)
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{
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int n = 0;
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struct perf_counter *counter;
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if (!is_software_counter(group)) {
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if (n >= max_count)
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return -1;
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ctrs[n] = group;
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events[n++] = group->hw.config;
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}
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list_for_each_entry(counter, &group->sibling_list, list_entry) {
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if (!is_software_counter(counter) &&
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counter->state != PERF_COUNTER_STATE_OFF) {
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if (n >= max_count)
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return -1;
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ctrs[n] = counter;
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events[n++] = counter->hw.config;
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}
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}
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return n;
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}
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|
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static void counter_sched_in(struct perf_counter *counter, int cpu)
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{
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counter->state = PERF_COUNTER_STATE_ACTIVE;
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counter->oncpu = cpu;
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if (is_software_counter(counter))
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counter->hw_ops->enable(counter);
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}
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|
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/*
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* Called to enable a whole group of counters.
|
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* Returns 1 if the group was enabled, or -EAGAIN if it could not be.
|
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* Assumes the caller has disabled interrupts and has
|
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* frozen the PMU with hw_perf_save_disable.
|
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*/
|
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int hw_perf_group_sched_in(struct perf_counter *group_leader,
|
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struct perf_cpu_context *cpuctx,
|
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struct perf_counter_context *ctx, int cpu)
|
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{
|
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struct cpu_hw_counters *cpuhw;
|
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long i, n, n0;
|
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struct perf_counter *sub;
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|
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cpuhw = &__get_cpu_var(cpu_hw_counters);
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n0 = cpuhw->n_counters;
|
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n = collect_events(group_leader, ppmu->n_counter - n0,
|
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&cpuhw->counter[n0], &cpuhw->events[n0]);
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if (n < 0)
|
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return -EAGAIN;
|
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if (check_excludes(cpuhw->counter, n0, n))
|
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return -EAGAIN;
|
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if (power_check_constraints(cpuhw->events, n + n0))
|
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return -EAGAIN;
|
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cpuhw->n_counters = n0 + n;
|
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cpuhw->n_added += n;
|
|
|
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/*
|
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* OK, this group can go on; update counter states etc.,
|
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* and enable any software counters
|
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*/
|
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for (i = n0; i < n0 + n; ++i)
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cpuhw->counter[i]->hw.config = cpuhw->events[i];
|
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cpuctx->active_oncpu += n;
|
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n = 1;
|
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counter_sched_in(group_leader, cpu);
|
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list_for_each_entry(sub, &group_leader->sibling_list, list_entry) {
|
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if (sub->state != PERF_COUNTER_STATE_OFF) {
|
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counter_sched_in(sub, cpu);
|
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++n;
|
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}
|
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}
|
|
ctx->nr_active += n;
|
|
|
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return 1;
|
|
}
|
|
|
|
/*
|
|
* Add a counter to the PMU.
|
|
* If all counters are not already frozen, then we disable and
|
|
* re-enable the PMU in order to get hw_perf_restore to do the
|
|
* actual work of reconfiguring the PMU.
|
|
*/
|
|
static int power_perf_enable(struct perf_counter *counter)
|
|
{
|
|
struct cpu_hw_counters *cpuhw;
|
|
unsigned long flags;
|
|
u64 pmudis;
|
|
int n0;
|
|
int ret = -EAGAIN;
|
|
|
|
local_irq_save(flags);
|
|
pmudis = hw_perf_save_disable();
|
|
|
|
/*
|
|
* Add the counter to the list (if there is room)
|
|
* and check whether the total set is still feasible.
|
|
*/
|
|
cpuhw = &__get_cpu_var(cpu_hw_counters);
|
|
n0 = cpuhw->n_counters;
|
|
if (n0 >= ppmu->n_counter)
|
|
goto out;
|
|
cpuhw->counter[n0] = counter;
|
|
cpuhw->events[n0] = counter->hw.config;
|
|
if (check_excludes(cpuhw->counter, n0, 1))
|
|
goto out;
|
|
if (power_check_constraints(cpuhw->events, n0 + 1))
|
|
goto out;
|
|
|
|
counter->hw.config = cpuhw->events[n0];
|
|
++cpuhw->n_counters;
|
|
++cpuhw->n_added;
|
|
|
|
ret = 0;
|
|
out:
|
|
hw_perf_restore(pmudis);
|
|
local_irq_restore(flags);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Remove a counter from the PMU.
|
|
*/
|
|
static void power_perf_disable(struct perf_counter *counter)
|
|
{
|
|
struct cpu_hw_counters *cpuhw;
|
|
long i;
|
|
u64 pmudis;
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
pmudis = hw_perf_save_disable();
|
|
|
|
power_perf_read(counter);
|
|
|
|
cpuhw = &__get_cpu_var(cpu_hw_counters);
|
|
for (i = 0; i < cpuhw->n_counters; ++i) {
|
|
if (counter == cpuhw->counter[i]) {
|
|
while (++i < cpuhw->n_counters)
|
|
cpuhw->counter[i-1] = cpuhw->counter[i];
|
|
--cpuhw->n_counters;
|
|
ppmu->disable_pmc(counter->hw.idx - 1, cpuhw->mmcr);
|
|
write_pmc(counter->hw.idx, 0);
|
|
counter->hw.idx = 0;
|
|
break;
|
|
}
|
|
}
|
|
if (cpuhw->n_counters == 0) {
|
|
/* disable exceptions if no counters are running */
|
|
cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
|
|
}
|
|
|
|
hw_perf_restore(pmudis);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
struct hw_perf_counter_ops power_perf_ops = {
|
|
.enable = power_perf_enable,
|
|
.disable = power_perf_disable,
|
|
.read = power_perf_read
|
|
};
|
|
|
|
const struct hw_perf_counter_ops *
|
|
hw_perf_counter_init(struct perf_counter *counter)
|
|
{
|
|
unsigned long ev;
|
|
struct perf_counter *ctrs[MAX_HWCOUNTERS];
|
|
unsigned int events[MAX_HWCOUNTERS];
|
|
int n;
|
|
|
|
if (!ppmu)
|
|
return NULL;
|
|
if ((s64)counter->hw_event.irq_period < 0)
|
|
return NULL;
|
|
ev = counter->hw_event.event_id;
|
|
if (!counter->hw_event.raw) {
|
|
if (ev >= ppmu->n_generic ||
|
|
ppmu->generic_events[ev] == 0)
|
|
return NULL;
|
|
ev = ppmu->generic_events[ev];
|
|
}
|
|
counter->hw.config_base = ev;
|
|
counter->hw.idx = 0;
|
|
|
|
/*
|
|
* If we are not running on a hypervisor, force the
|
|
* exclude_hv bit to 0 so that we don't care what
|
|
* the user set it to.
|
|
*/
|
|
if (!firmware_has_feature(FW_FEATURE_LPAR))
|
|
counter->hw_event.exclude_hv = 0;
|
|
|
|
/*
|
|
* If this is in a group, check if it can go on with all the
|
|
* other hardware counters in the group. We assume the counter
|
|
* hasn't been linked into its leader's sibling list at this point.
|
|
*/
|
|
n = 0;
|
|
if (counter->group_leader != counter) {
|
|
n = collect_events(counter->group_leader, ppmu->n_counter - 1,
|
|
ctrs, events);
|
|
if (n < 0)
|
|
return NULL;
|
|
}
|
|
events[n] = ev;
|
|
ctrs[n] = counter;
|
|
if (check_excludes(ctrs, n, 1))
|
|
return NULL;
|
|
if (power_check_constraints(events, n + 1))
|
|
return NULL;
|
|
|
|
counter->hw.config = events[n];
|
|
atomic64_set(&counter->hw.period_left, counter->hw_event.irq_period);
|
|
return &power_perf_ops;
|
|
}
|
|
|
|
/*
|
|
* Handle wakeups.
|
|
*/
|
|
void perf_counter_do_pending(void)
|
|
{
|
|
int i;
|
|
struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters);
|
|
struct perf_counter *counter;
|
|
|
|
for (i = 0; i < cpuhw->n_counters; ++i) {
|
|
counter = cpuhw->counter[i];
|
|
if (counter && counter->wakeup_pending) {
|
|
counter->wakeup_pending = 0;
|
|
wake_up(&counter->waitq);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* A counter has overflowed; update its count and record
|
|
* things if requested. Note that interrupts are hard-disabled
|
|
* here so there is no possibility of being interrupted.
|
|
*/
|
|
static void record_and_restart(struct perf_counter *counter, long val,
|
|
struct pt_regs *regs)
|
|
{
|
|
s64 prev, delta, left;
|
|
int record = 0;
|
|
|
|
/* we don't have to worry about interrupts here */
|
|
prev = atomic64_read(&counter->hw.prev_count);
|
|
delta = (val - prev) & 0xfffffffful;
|
|
atomic64_add(delta, &counter->count);
|
|
|
|
/*
|
|
* See if the total period for this counter has expired,
|
|
* and update for the next period.
|
|
*/
|
|
val = 0;
|
|
left = atomic64_read(&counter->hw.period_left) - delta;
|
|
if (counter->hw_event.irq_period) {
|
|
if (left <= 0) {
|
|
left += counter->hw_event.irq_period;
|
|
if (left <= 0)
|
|
left = counter->hw_event.irq_period;
|
|
record = 1;
|
|
}
|
|
if (left < 0x80000000L)
|
|
val = 0x80000000L - left;
|
|
}
|
|
write_pmc(counter->hw.idx, val);
|
|
atomic64_set(&counter->hw.prev_count, val);
|
|
atomic64_set(&counter->hw.period_left, left);
|
|
|
|
/*
|
|
* Finally record data if requested.
|
|
*/
|
|
if (record)
|
|
perf_counter_output(counter, 1, regs);
|
|
}
|
|
|
|
/*
|
|
* Performance monitor interrupt stuff
|
|
*/
|
|
static void perf_counter_interrupt(struct pt_regs *regs)
|
|
{
|
|
int i;
|
|
struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters);
|
|
struct perf_counter *counter;
|
|
long val;
|
|
int need_wakeup = 0, found = 0;
|
|
|
|
for (i = 0; i < cpuhw->n_counters; ++i) {
|
|
counter = cpuhw->counter[i];
|
|
val = read_pmc(counter->hw.idx);
|
|
if ((int)val < 0) {
|
|
/* counter has overflowed */
|
|
found = 1;
|
|
record_and_restart(counter, val, regs);
|
|
if (counter->wakeup_pending)
|
|
need_wakeup = 1;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* In case we didn't find and reset the counter that caused
|
|
* the interrupt, scan all counters and reset any that are
|
|
* negative, to avoid getting continual interrupts.
|
|
* Any that we processed in the previous loop will not be negative.
|
|
*/
|
|
if (!found) {
|
|
for (i = 0; i < ppmu->n_counter; ++i) {
|
|
val = read_pmc(i + 1);
|
|
if ((int)val < 0)
|
|
write_pmc(i + 1, 0);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Reset MMCR0 to its normal value. This will set PMXE and
|
|
* clear FC (freeze counters) and PMAO (perf mon alert occurred)
|
|
* and thus allow interrupts to occur again.
|
|
* XXX might want to use MSR.PM to keep the counters frozen until
|
|
* we get back out of this interrupt.
|
|
*/
|
|
mtspr(SPRN_MMCR0, cpuhw->mmcr[0]);
|
|
|
|
/*
|
|
* If we need a wakeup, check whether interrupts were soft-enabled
|
|
* when we took the interrupt. If they were, we can wake stuff up
|
|
* immediately; otherwise we'll have to set a flag and do the
|
|
* wakeup when interrupts get soft-enabled.
|
|
*/
|
|
if (need_wakeup) {
|
|
if (regs->softe) {
|
|
irq_enter();
|
|
perf_counter_do_pending();
|
|
irq_exit();
|
|
} else {
|
|
set_perf_counter_pending();
|
|
}
|
|
}
|
|
}
|
|
|
|
void hw_perf_counter_setup(int cpu)
|
|
{
|
|
struct cpu_hw_counters *cpuhw = &per_cpu(cpu_hw_counters, cpu);
|
|
|
|
memset(cpuhw, 0, sizeof(*cpuhw));
|
|
cpuhw->mmcr[0] = MMCR0_FC;
|
|
}
|
|
|
|
extern struct power_pmu power4_pmu;
|
|
extern struct power_pmu ppc970_pmu;
|
|
extern struct power_pmu power5_pmu;
|
|
extern struct power_pmu power5p_pmu;
|
|
extern struct power_pmu power6_pmu;
|
|
|
|
static int init_perf_counters(void)
|
|
{
|
|
unsigned long pvr;
|
|
|
|
if (reserve_pmc_hardware(perf_counter_interrupt)) {
|
|
printk(KERN_ERR "Couldn't init performance monitor subsystem\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
/* XXX should get this from cputable */
|
|
pvr = mfspr(SPRN_PVR);
|
|
switch (PVR_VER(pvr)) {
|
|
case PV_POWER4:
|
|
case PV_POWER4p:
|
|
ppmu = &power4_pmu;
|
|
break;
|
|
case PV_970:
|
|
case PV_970FX:
|
|
case PV_970MP:
|
|
ppmu = &ppc970_pmu;
|
|
break;
|
|
case PV_POWER5:
|
|
ppmu = &power5_pmu;
|
|
break;
|
|
case PV_POWER5p:
|
|
ppmu = &power5p_pmu;
|
|
break;
|
|
case 0x3e:
|
|
ppmu = &power6_pmu;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Use FCHV to ignore kernel events if MSR.HV is set.
|
|
*/
|
|
if (mfmsr() & MSR_HV)
|
|
freeze_counters_kernel = MMCR0_FCHV;
|
|
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(init_perf_counters);
|