Rafał Miłecki 04ad1fb264 ssb: update reject bit for Target State Low ... My 14e4:4315 is SSB_IDLOW_SSBREV_26: read32 0xfaafcff8 -> 0x600422d5 My 14e4:4328 is SSB_IDLOW_SSBREV_24: read32 0xfaafcff8 -> 0x400422c5 My 14e4:432b is SSB_IDLOW_SSBREV_26 again: read32 0xfaafcff8 -> 0x600422d5 For all of them wl driver is using 0x2 reject bit: write32(0xf98) <- 0x00010002 So it seems SSB 2.3 is the exception using another bit. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>		2011-04-26 15:50:29 -04:00
..
b43_pci_bridge.c
driver_chipcommon_pmu.c	ssb: cc: use correct min_msk for 0x4312	2011-04-25 14:50:13 -04:00
driver_chipcommon.c	ssb: cc: clear GPIOPULL registers on init	2011-04-25 14:50:20 -04:00
driver_extif.c
driver_gige.c
driver_mipscore.c
driver_pcicore.c	ssb: pci: trivial: correct amount of maximum retries	2011-04-25 14:50:13 -04:00
embedded.c
Kconfig
main.c	ssb: update reject bit for Target State Low	2011-04-26 15:50:29 -04:00
Makefile
pci.c	ssb: trivial: fix SPROM extract warning formatting	2011-02-18 16:54:52 -05:00
pcihost_wrapper.c
pcmcia.c
scan.c	ssb: trivial: use u8 for chip_rev (it's mask is 0xF)	2011-04-04 16:20:06 -04:00
sdio.c
sprom.c
ssb_private.h