linux/arch/powerpc/mm
Suzuki Poulose 368ff8f14d powerpc: Define virtual-physical translations for RELOCATABLE
We find the runtime address of _stext and relocate ourselves based
on the following calculation.

	virtual_base = ALIGN(KERNELBASE,KERNEL_TLB_PIN_SIZE) +
			MODULO(_stext.run,KERNEL_TLB_PIN_SIZE)

relocate() is called with the Effective Virtual Base Address (as
shown below)

            | Phys. Addr| Virt. Addr |
Page        |------------------------|
Boundary    |           |            |
            |           |            |
            |           |            |
Kernel Load |___________|_ __ _ _ _ _|<- Effective
Addr(_stext)|           |      ^     |Virt. Base Addr
            |           |      |     |
            |           |      |     |
            |           |reloc_offset|
            |           |      |     |
            |           |      |     |
            |           |______v_____|<-(KERNELBASE)%TLB_SIZE
            |           |            |
            |           |            |
            |           |            |
Page        |-----------|------------|
Boundary    |           |            |

On BookE, we need __va() & __pa() early in the boot process to access
the device tree.

Currently this has been defined as :

#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) -
						PHYSICAL_START + KERNELBASE)
where:
 PHYSICAL_START is kernstart_addr - a variable updated at runtime.
 KERNELBASE	is the compile time Virtual base address of kernel.

This won't work for us, as kernstart_addr is dynamic and will yield different
results for __va()/__pa() for same mapping.

e.g.,

Let the kernel be loaded at 64MB and KERNELBASE be 0xc0000000 (same as
PAGE_OFFSET).

In this case, we would be mapping 0 to 0xc0000000, and kernstart_addr = 64M

Now __va(1MB) = (0x100000) - (0x4000000) + 0xc0000000
		= 0xbc100000 , which is wrong.

it should be : 0xc0000000 + 0x100000 = 0xc0100000

On platforms which support AMP, like PPC_47x (based on 44x), the kernel
could be loaded at highmem. Hence we cannot always depend on the compile
time constants for mapping.

Here are the possible solutions:

1) Update kernstart_addr(PHSYICAL_START) to match the Physical address of
compile time KERNELBASE value, instead of the actual Physical_Address(_stext).

The disadvantage is that we may break other users of PHYSICAL_START. They
could be replaced with __pa(_stext).

2) Redefine __va() & __pa() with relocation offset

#ifdef	CONFIG_RELOCATABLE_PPC32
#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) - PHYSICAL_START + (KERNELBASE + RELOC_OFFSET)))
#define __pa(x) ((unsigned long)(x) + PHYSICAL_START - (KERNELBASE + RELOC_OFFSET))
#endif

where, RELOC_OFFSET could be

  a) A variable, say relocation_offset (like kernstart_addr), updated
     at boot time. This impacts performance, as we have to load an additional
     variable from memory.

		OR

  b) #define RELOC_OFFSET ((PHYSICAL_START & PPC_PIN_SIZE_OFFSET_MASK) - \
                      (KERNELBASE & PPC_PIN_SIZE_OFFSET_MASK))

   This introduces more calculations for doing the translation.

3) Redefine __va() & __pa() with a new variable

i.e,

#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + VIRT_PHYS_OFFSET))

where VIRT_PHYS_OFFSET :

#ifdef CONFIG_RELOCATABLE_PPC32
#define VIRT_PHYS_OFFSET virt_phys_offset
#else
#define VIRT_PHYS_OFFSET (KERNELBASE - PHYSICAL_START)
#endif /* CONFIG_RELOCATABLE_PPC32 */

where virt_phy_offset is updated at runtime to :

	Effective KERNELBASE - kernstart_addr.

Taking our example, above:

virt_phys_offset = effective_kernelstart_vaddr - kernstart_addr
		 = 0xc0400000 - 0x400000
		 = 0xc0000000
	and

	__va(0x100000) = 0xc0000000 + 0x100000 = 0xc0100000
	 which is what we want.

I have implemented (3) in the following patch which has same cost of
operation as the existing one.

I have tested the patches on 440x platforms only. However this should
work fine for PPC_47x also, as we only depend on the runtime address
and the current TLB XLAT entry for the startup code, which is available
in r25. I don't have access to a 47x board yet. So, it would be great if
somebody could test this on 47x.

Signed-off-by: Suzuki K. Poulose <suzuki@in.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Signed-off-by: Josh Boyer <jwboyer@gmail.com>
2011-12-20 10:21:34 -05:00
..
40x_mmu.c
44x_mmu.c powerpc: Rename mapping based RELOCATABLE to DYNAMIC_MEMSTART for BookE 2011-12-20 10:20:19 -05:00
dma-noncoherent.c powerpc: include export.h for files using EXPORT_SYMBOL/THIS_MODULE 2011-10-31 19:30:38 -04:00
fault.c powerpc/icswx: Simple ACOP fault handler 2011-11-25 14:11:28 +11:00
fsl_booke_mmu.c powerpc/fsl-booke: Fix settlbcam for 64-bit 2011-10-12 23:39:10 -05:00
gup.c powerpc: remove superfluous PageTail checks on the pte gup_fast 2011-11-02 16:06:57 -07:00
hash_low_32.S
hash_low_64.S powerpc: Free up some CPU feature bits by moving out MMU-related features 2011-04-27 14:18:52 +10:00
hash_native_64.c KVM: PPC: book3s_hv: Add support for PPC970-family processors 2011-07-12 13:16:59 +03:00
hash_utils_64.c Merge branch 'modsplit-Oct31_2011' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux 2011-11-06 19:44:47 -08:00
highmem.c
hugetlbpage-book3e.c powerpc/book3e: Change hugetlb preload to take vma argument 2011-12-07 16:26:24 +11:00
hugetlbpage-hash64.c
hugetlbpage.c powerpc: Add gpages reservation code for 64-bit FSL BOOKE 2011-12-07 16:26:23 +11:00
icswx_pid.c powerpc: Split ICSWX ACOP and PID processing 2011-11-25 14:11:27 +11:00
icswx.c powerpc/icswx: Simple ACOP fault handler 2011-11-25 14:11:28 +11:00
icswx.h powerpc/icswx: Simple ACOP fault handler 2011-11-25 14:11:28 +11:00
init_32.c powerpc: Define virtual-physical translations for RELOCATABLE 2011-12-20 10:21:34 -05:00
init_64.c powerpc: Move free_initmem to common code 2011-06-30 15:28:05 +10:00
Makefile powerpc: Split ICSWX ACOP and PID processing 2011-11-25 14:11:27 +11:00
mem.c powerpc: Punch a hole in /dev/mem for librtas 2011-12-08 14:22:52 +11:00
mmap_64.c powerpc+sparc64/mm: Remove hack in mmap randomize layout 2011-11-28 11:42:09 +11:00
mmu_context_hash32.c powerpc: include export.h for files using EXPORT_SYMBOL/THIS_MODULE 2011-10-31 19:30:38 -04:00
mmu_context_hash64.c powerpc: Split ICSWX ACOP and PID processing 2011-11-25 14:11:27 +11:00
mmu_context_nohash.c powerpc: Hugetlb for BookE 2011-09-20 09:19:40 +10:00
mmu_decl.h powerpc/fsl-booke: Fix setup_initial_memory_limit to not blindly map 2011-10-11 23:30:41 -05:00
numa.c powerpc/mm: Fix section mismatch for read_n_cells 2011-12-19 14:41:18 +11:00
pgtable_32.c powerpc: Remove ioremap_flags 2011-05-19 14:30:43 +10:00
pgtable_64.c powerpc: add export.h to files making use of EXPORT_SYMBOL 2011-10-31 19:30:37 -04:00
pgtable.c powerpc: Hugetlb for BookE 2011-09-20 09:19:40 +10:00
ppc_mmu_32.c
slb_low.S powerpc: Free up some CPU feature bits by moving out MMU-related features 2011-04-27 14:18:52 +10:00
slb.c powerpc: Free up some CPU feature bits by moving out MMU-related features 2011-04-27 14:18:52 +10:00
slice.c powerpc: various straight conversions from module.h --> export.h 2011-10-31 19:30:44 -04:00
stab.c powerpc: Free up some CPU feature bits by moving out MMU-related features 2011-04-27 14:18:52 +10:00
subpage-prot.c
tlb_hash32.c powerpc: include export.h for files using EXPORT_SYMBOL/THIS_MODULE 2011-10-31 19:30:38 -04:00
tlb_hash64.c mm, powerpc: move the RCU page-table freeing into generic code 2011-05-25 08:39:16 -07:00
tlb_low_64e.S powerpc: Add hugepage support to 64-bit tablewalk code for FSL_BOOK3E 2011-12-07 16:26:22 +11:00
tlb_nohash_low.S
tlb_nohash.c powerpc: hugetlb: modify include usage for FSL BookE code 2011-12-07 16:26:22 +11:00