248 lines
6.1 KiB
C
248 lines
6.1 KiB
C
/*
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* Marvell Kirkwood SoC clocks
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "common.h"
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/*
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* Core Clocks
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*
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* Kirkwood PLL sample-at-reset configuration
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* (6180 has different SAR layout than other Kirkwood SoCs)
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*
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* SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
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* 4 = 600 MHz
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* 6 = 800 MHz
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* 7 = 1000 MHz
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* 9 = 1200 MHz
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* 12 = 1500 MHz
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* 13 = 1600 MHz
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* 14 = 1800 MHz
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* 15 = 2000 MHz
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* others reserved.
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*
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* SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
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* 1 = (1/2) * CPU
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* 3 = (1/3) * CPU
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* 5 = (1/4) * CPU
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* others reserved.
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*
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* SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
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* 2 = (1/2) * CPU
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* 4 = (1/3) * CPU
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* 6 = (1/4) * CPU
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* 7 = (2/9) * CPU
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* 8 = (1/5) * CPU
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* 9 = (1/6) * CPU
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* others reserved.
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*
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* SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
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* 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
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* 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
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* 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
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* others reserved.
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*
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* SAR0[21] : TCLK frequency
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* 0 = 200 MHz
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* 1 = 166 MHz
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* others reserved.
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*/
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#define SAR_KIRKWOOD_CPU_FREQ(x) \
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(((x & (1 << 1)) >> 1) | \
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((x & (1 << 22)) >> 21) | \
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((x & (3 << 3)) >> 1))
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#define SAR_KIRKWOOD_L2_RATIO(x) \
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(((x & (3 << 9)) >> 9) | \
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(((x & (1 << 19)) >> 17)))
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#define SAR_KIRKWOOD_DDR_RATIO 5
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#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
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#define SAR_MV88F6180_CLK 2
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#define SAR_MV88F6180_CLK_MASK 0x7
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#define SAR_KIRKWOOD_TCLK_FREQ 21
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#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
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enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
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static const struct coreclk_ratio __initconst kirkwood_coreclk_ratios[] = {
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{ .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
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{ .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
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};
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static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
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{
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u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
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SAR_KIRKWOOD_TCLK_FREQ_MASK;
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return (opt) ? 166666667 : 200000000;
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}
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static const u32 __initconst kirkwood_cpu_freqs[] = {
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0, 0, 0, 0,
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600000000,
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0,
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800000000,
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1000000000,
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0,
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1200000000,
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0, 0,
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1500000000,
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1600000000,
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1800000000,
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2000000000
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};
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static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
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{
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u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
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return kirkwood_cpu_freqs[opt];
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}
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static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
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{ 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
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{ 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
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};
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static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
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{ 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
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{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
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{ 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
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{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
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};
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static void __init kirkwood_get_clk_ratio(
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void __iomem *sar, int id, int *mult, int *div)
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{
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switch (id) {
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case KIRKWOOD_CPU_TO_L2:
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{
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u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
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*mult = kirkwood_cpu_l2_ratios[opt][0];
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*div = kirkwood_cpu_l2_ratios[opt][1];
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break;
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}
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case KIRKWOOD_CPU_TO_DDR:
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{
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u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
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SAR_KIRKWOOD_DDR_RATIO_MASK;
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*mult = kirkwood_cpu_ddr_ratios[opt][0];
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*div = kirkwood_cpu_ddr_ratios[opt][1];
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break;
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}
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}
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}
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static const u32 __initconst mv88f6180_cpu_freqs[] = {
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0, 0, 0, 0, 0,
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600000000,
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800000000,
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1000000000
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};
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static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
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{
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u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
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return mv88f6180_cpu_freqs[opt];
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}
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static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
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{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
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{ 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
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};
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static void __init mv88f6180_get_clk_ratio(
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void __iomem *sar, int id, int *mult, int *div)
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{
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switch (id) {
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case KIRKWOOD_CPU_TO_L2:
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{
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/* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
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*mult = 1;
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*div = 2;
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break;
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}
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case KIRKWOOD_CPU_TO_DDR:
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{
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u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
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SAR_MV88F6180_CLK_MASK;
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*mult = mv88f6180_cpu_ddr_ratios[opt][0];
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*div = mv88f6180_cpu_ddr_ratios[opt][1];
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break;
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}
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}
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}
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static const struct coreclk_soc_desc kirkwood_coreclks = {
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.get_tclk_freq = kirkwood_get_tclk_freq,
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.get_cpu_freq = kirkwood_get_cpu_freq,
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.get_clk_ratio = kirkwood_get_clk_ratio,
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.ratios = kirkwood_coreclk_ratios,
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.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
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};
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static void __init kirkwood_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &kirkwood_coreclks);
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}
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CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock",
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kirkwood_coreclk_init);
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static const struct coreclk_soc_desc mv88f6180_coreclks = {
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.get_tclk_freq = kirkwood_get_tclk_freq,
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.get_cpu_freq = mv88f6180_get_cpu_freq,
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.get_clk_ratio = mv88f6180_get_clk_ratio,
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.ratios = kirkwood_coreclk_ratios,
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.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
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};
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static void __init mv88f6180_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &mv88f6180_coreclks);
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}
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CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
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mv88f6180_coreclk_init);
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/*
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* Clock Gating Control
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*/
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static const struct clk_gating_soc_desc __initconst kirkwood_gating_desc[] = {
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{ "ge0", NULL, 0, 0 },
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{ "pex0", NULL, 2, 0 },
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{ "usb0", NULL, 3, 0 },
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{ "sdio", NULL, 4, 0 },
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{ "tsu", NULL, 5, 0 },
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{ "runit", NULL, 7, 0 },
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{ "xor0", NULL, 8, 0 },
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{ "audio", NULL, 9, 0 },
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{ "powersave", "cpuclk", 11, 0 },
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{ "sata0", NULL, 14, 0 },
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{ "sata1", NULL, 15, 0 },
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{ "xor1", NULL, 16, 0 },
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{ "crypto", NULL, 17, 0 },
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{ "pex1", NULL, 18, 0 },
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{ "ge1", NULL, 19, 0 },
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{ "tdm", NULL, 20, 0 },
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{ }
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};
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static void __init kirkwood_clk_gating_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, kirkwood_gating_desc);
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}
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CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock",
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kirkwood_clk_gating_init);
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