Zong Li 927cc45771 riscv: ftrace: correct the condition logic in function graph tracer ... commit 1d8f657982 upstream. The condition should be logical NOT to assign the hook address to parent address. Because the return value 0 of function_graph_enter upon success. Fixes: e949b6db51 (riscv/function_graph: Simplify with function_graph_enter()) Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Steven Rostedt (VMware) <rostedt@goodmis.org> Cc: stable@vger.kernel.org Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2020-01-09 10:19:59 +01:00
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boot	riscv: dts: HiFive Unleashed: add default chosen/stdout-path	2019-10-14 12:30:30 -07:00
configs	RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig	2019-09-19 05:44:35 -07:00
include	RISC-V: Add PCIe I/O BAR memory mapping	2019-10-28 10:43:32 -07:00
kernel	riscv: ftrace: correct the condition logic in function graph tracer	2020-01-09 10:19:59 +01:00
lib	riscv: Using CSR numbers to access CSRs	2019-08-30 11:04:19 -07:00
mm	riscv: add missing header file includes	2019-10-28 00:46:01 -07:00
net	bpf, riscv: Enable zext optimization for more RV64G ALU ops	2019-07-05 23:55:41 +02:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: make mmap allocation top-down by default	2019-09-24 15:54:12 -07:00
Kconfig.debug	…
Kconfig.socs	riscv: select SiFive platform drivers with SOC_SIFIVE	2019-07-01 13:20:01 -07:00
Makefile	Kbuild updates for v5.4	2019-09-20 08:36:47 -07:00