d8005e6b95
ARC700 includes 2 in-core 32bit timers TIMER0 and TIMER1.
Both have exactly same capabilies.
* programmable to count from TIMER<n>_CNT to TIMER<n>_LIMIT
* for count 0 and LIMIT ~1, provides a free-running counter by
auto-wrapping when limit is reached.
* optionally interrupt when LIMIT is reached (oneshot event semantics)
* rearming the interrupt provides periodic semantics
* run at CPU clk
ARC Linux uses TIMER0 for clockevent (periodic/oneshot) and TIMER1 for
clocksource (free-running clock).
Newer cores provide RTSC insn which gives a 64bit cpu clk snapshot hence
is more apt for clocksource when available.
SMP poses a bit of challenge for global timekeeping clocksource /
sched_clock() backend:
-TIMER1 based local clocks are out-of-sync hence can't be used
(thus we default to jiffies based cs as well as sched_clock() one/both
of which platform can override with it's specific hardware assist)
-RTSC is only allowed in SMP if it's cross-core-sync (Kconfig glue
ensures that) and thus usable for both requirements.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Delay routines using pre computed loops_per_jiffy value.
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*
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* vineetg: Feb 2012
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* -Rewrote in "C" to avoid dealing with availability of H/w MPY
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* -Also reduced the num of MPY operations from 3 to 2
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*
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* Amit Bhor: Codito Technologies 2004
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*/
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#ifndef __ASM_ARC_UDELAY_H
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#define __ASM_ARC_UDELAY_H
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#include <asm/param.h> /* HZ */
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static inline void __delay(unsigned long loops)
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{
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__asm__ __volatile__(
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"1: sub.f %0, %0, 1 \n"
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" jpnz 1b \n"
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: "+r"(loops)
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:
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: "cc");
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}
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extern void __bad_udelay(void);
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/*
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* Normal Math for computing loops in "N" usecs
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* -we have precomputed @loops_per_jiffy
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* -1 sec has HZ jiffies
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* loops per "N" usecs = ((loops_per_jiffy * HZ / 1000000) * N)
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*
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* Approximate Division by multiplication:
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* -Mathematically if we multiply and divide a number by same value the
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* result remains unchanged: In this case, we use 2^32
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* -> (loops_per_N_usec * 2^32 ) / 2^32
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* -> (((loops_per_jiffy * HZ / 1000000) * N) * 2^32) / 2^32
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* -> (loops_per_jiffy * HZ * N * 4295) / 2^32
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*
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* -Divide by 2^32 is very simply right shift by 32
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* -We simply need to ensure that the multiply per above eqn happens in
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* 64-bit precision (if CPU doesn't support it - gcc can emaulate it)
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*/
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static inline void __udelay(unsigned long usecs)
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{
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unsigned long loops;
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/* (long long) cast ensures 64 bit MPY - real or emulated
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* HZ * 4295 is pre-evaluated by gcc - hence only 2 mpy ops
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*/
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loops = ((long long)(usecs * 4295 * HZ) *
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(long long)(loops_per_jiffy)) >> 32;
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__delay(loops);
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}
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#define udelay(n) (__builtin_constant_p(n) ? ((n) > 20000 ? __bad_udelay() \
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: __udelay(n)) : __udelay(n))
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#endif /* __ASM_ARC_UDELAY_H */
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