45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/*
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* Common defines for v7m cpus
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*/
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#define V7M_SCS_ICTR IOMEM(0xe000e004)
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#define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
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#define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
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#define V7M_SCB_CPUID 0x00
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#define V7M_SCB_ICSR 0x04
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#define V7M_SCB_ICSR_PENDSVSET (1 << 28)
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#define V7M_SCB_ICSR_PENDSVCLR (1 << 27)
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#define V7M_SCB_ICSR_RETTOBASE (1 << 11)
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#define V7M_SCB_VTOR 0x08
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#define V7M_SCB_SCR 0x10
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#define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
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#define V7M_SCB_CCR 0x14
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#define V7M_SCB_CCR_STKALIGN (1 << 9)
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#define V7M_SCB_SHPR2 0x1c
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#define V7M_SCB_SHPR3 0x20
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#define V7M_SCB_SHCSR 0x24
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#define V7M_SCB_SHCSR_USGFAULTENA (1 << 18)
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#define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17)
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#define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16)
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#define V7M_xPSR_FRAMEPTRALIGN 0x00000200
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#define V7M_xPSR_EXCEPTIONNO 0x000001ff
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/*
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* When branching to an address that has bits [31:28] == 0xf an exception return
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* occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
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* extension Bit [4] defines if the exception frame has space allocated for FP
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* state information, SBOP otherwise. Bit [3] defines the mode that is returned
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* to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
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* (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
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*/
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#define EXC_RET_STACK_MASK 0x00000004
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#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd
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