4c61a1e75c
Currently the cpufreq volt/freq table we used is for LDO enable mode, according to latest datasheet Rev. 3, 03/2014, the volt/freq table is as below: LDO enabled(min value): 996MHz: VDDARM: 1.225V, VDDSOC: 1.150V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 1.050V, VDDSOC: 1.150V; LDO bypassed(min value): 996MHz: VDDARM: 1.250V, VDDSOC: 1.150V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 1.050V, VDDSOC: 1.150V; Adding 25mV to cover board IR drop, for LDO enabled mode of 996MHz, VDDARM should be 1.250V, so this patch updates it. Signed-off-by: Anson Huang <b20788@freescale.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
125 lines
2.6 KiB
Plaintext
125 lines
2.6 KiB
Plaintext
|
|
/*
|
|
* Copyright 2013 Freescale Semiconductor, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include "imx6dl-pinfunc.h"
|
|
#include "imx6qdl.dtsi"
|
|
|
|
/ {
|
|
aliases {
|
|
i2c3 = &i2c4;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a9";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
next-level-cache = <&L2>;
|
|
operating-points = <
|
|
/* kHz uV */
|
|
996000 1250000
|
|
792000 1175000
|
|
396000 1075000
|
|
>;
|
|
fsl,soc-operating-points = <
|
|
/* ARM kHz SOC-PU uV */
|
|
996000 1175000
|
|
792000 1175000
|
|
396000 1175000
|
|
>;
|
|
clock-latency = <61036>; /* two CLK32 periods */
|
|
clocks = <&clks IMX6QDL_CLK_ARM>,
|
|
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
|
|
<&clks IMX6QDL_CLK_STEP>,
|
|
<&clks IMX6QDL_CLK_PLL1_SW>,
|
|
<&clks IMX6QDL_CLK_PLL1_SYS>;
|
|
clock-names = "arm", "pll2_pfd2_396m", "step",
|
|
"pll1_sw", "pll1_sys";
|
|
arm-supply = <®_arm>;
|
|
pu-supply = <®_pu>;
|
|
soc-supply = <®_soc>;
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "arm,cortex-a9";
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
ocram: sram@00900000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x00900000 0x20000>;
|
|
clocks = <&clks IMX6QDL_CLK_OCRAM>;
|
|
};
|
|
|
|
aips1: aips-bus@02000000 {
|
|
iomuxc: iomuxc@020e0000 {
|
|
compatible = "fsl,imx6dl-iomuxc";
|
|
};
|
|
|
|
pxp: pxp@020f0000 {
|
|
reg = <0x020f0000 0x4000>;
|
|
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
epdc: epdc@020f4000 {
|
|
reg = <0x020f4000 0x4000>;
|
|
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
lcdif: lcdif@020f8000 {
|
|
reg = <0x020f8000 0x4000>;
|
|
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
aips2: aips-bus@02100000 {
|
|
i2c4: i2c@021f8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021f8000 0x4000>;
|
|
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6DL_CLK_I2C4>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
display-subsystem {
|
|
compatible = "fsl,imx-display-subsystem";
|
|
ports = <&ipu1_di0>, <&ipu1_di1>;
|
|
};
|
|
};
|
|
|
|
&hdmi {
|
|
compatible = "fsl,imx6dl-hdmi";
|
|
};
|
|
|
|
&ldb {
|
|
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
|
|
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
|
|
<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
|
|
clock-names = "di0_pll", "di1_pll",
|
|
"di0_sel", "di1_sel",
|
|
"di0", "di1";
|
|
};
|
|
|
|
&vpu {
|
|
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
|
|
};
|