132 lines
3.5 KiB
C
132 lines
3.5 KiB
C
/*
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* Meta cache partition manipulation.
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*
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* Copyright 2010 Imagination Technologies Ltd.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <asm/processor.h>
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#include <asm/cachepart.h>
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#include <asm/metag_isa.h>
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#include <asm/metag_mem.h>
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#define SYSC_DCPART(n) (SYSC_DCPART0 + SYSC_xCPARTn_STRIDE * (n))
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#define SYSC_ICPART(n) (SYSC_ICPART0 + SYSC_xCPARTn_STRIDE * (n))
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#define CACHE_ASSOCIATIVITY 4 /* 4 way set-assosiative */
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#define ICACHE 0
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#define DCACHE 1
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/* The CORE_CONFIG2 register is not available on Meta 1 */
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#ifdef CONFIG_METAG_META21
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unsigned int get_dcache_size(void)
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{
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unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
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unsigned int sz = 0x1000 << ((config2 & METAC_CORECFG2_DCSZ_BITS)
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>> METAC_CORECFG2_DCSZ_S);
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if (config2 & METAC_CORECFG2_DCSMALL_BIT)
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sz >>= 6;
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return sz;
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}
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unsigned int get_icache_size(void)
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{
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unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
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unsigned int sz = 0x1000 << ((config2 & METAC_CORE_C2ICSZ_BITS)
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>> METAC_CORE_C2ICSZ_S);
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if (config2 & METAC_CORECFG2_ICSMALL_BIT)
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sz >>= 6;
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return sz;
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}
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unsigned int get_global_dcache_size(void)
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{
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unsigned int cpart = metag_in32(SYSC_DCPART(hard_processor_id()));
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unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
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return (get_dcache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
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}
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unsigned int get_global_icache_size(void)
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{
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unsigned int cpart = metag_in32(SYSC_ICPART(hard_processor_id()));
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unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
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return (get_icache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
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}
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static int get_thread_cache_size(unsigned int cache, int thread_id)
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{
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unsigned int cache_size;
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unsigned int t_cache_part;
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unsigned int isEnabled;
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unsigned int offset = 0;
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isEnabled = (cache == DCACHE ? metag_in32(MMCU_DCACHE_CTRL_ADDR) & 0x1 :
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metag_in32(MMCU_ICACHE_CTRL_ADDR) & 0x1);
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if (!isEnabled)
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return 0;
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#if PAGE_OFFSET >= LINGLOBAL_BASE
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/* Checking for global cache */
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cache_size = (cache == DCACHE ? get_global_dcache_size() :
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get_global_icache_size());
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offset = 8;
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#else
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cache_size = (cache == DCACHE ? get_dcache_size() :
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get_icache_size());
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#endif
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t_cache_part = (cache == DCACHE ?
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(metag_in32(SYSC_DCPART(thread_id)) >> offset) & 0xF :
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(metag_in32(SYSC_ICPART(thread_id)) >> offset) & 0xF);
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switch (t_cache_part) {
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case 0xF:
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return cache_size;
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case 0x7:
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return cache_size / 2;
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case 0x3:
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return cache_size / 4;
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case 0x1:
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return cache_size / 8;
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case 0:
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return cache_size / 16;
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}
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return -1;
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}
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void check_for_cache_aliasing(int thread_id)
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{
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int thread_cache_size;
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unsigned int cache_type;
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for (cache_type = ICACHE; cache_type <= DCACHE; cache_type++) {
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thread_cache_size =
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get_thread_cache_size(cache_type, thread_id);
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if (thread_cache_size < 0)
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pr_emerg("Can't read %s cache size\n",
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cache_type ? "DCACHE" : "ICACHE");
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else if (thread_cache_size == 0)
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/* Cache is off. No need to check for aliasing */
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continue;
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if (thread_cache_size / CACHE_ASSOCIATIVITY > PAGE_SIZE) {
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pr_emerg("Potential cache aliasing detected in %s on Thread %d\n",
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cache_type ? "DCACHE" : "ICACHE", thread_id);
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pr_warn("Total %s size: %u bytes\n",
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cache_type ? "DCACHE" : "ICACHE",
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cache_type ? get_dcache_size()
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: get_icache_size());
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pr_warn("Thread %s size: %d bytes\n",
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cache_type ? "CACHE" : "ICACHE",
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thread_cache_size);
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pr_warn("Page Size: %lu bytes\n", PAGE_SIZE);
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panic("Potential cache aliasing detected");
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}
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}
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}
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#else
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void check_for_cache_aliasing(int thread_id)
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{
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return;
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}
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#endif
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