Russ Anderson 2022c1f136 [IA64] Update Altix nofault code ... Montecito and Montvale behaves slightly differently than previous Itanium processors, resulting in the MCA due to a failed PIO read to sometimes surfacing outside the nofault code. This code is based on discussions with Intel CPU architects and verified at customer sites. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>		2008-01-03 13:22:54 -08:00
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configs	[IA64] update sn2 defconfig to 64kb pages	2007-10-29 11:32:42 -07:00
dig	…
hp	[IA64] Guard elfcorehdr_addr with #if CONFIG_PROC_FS	2007-12-19 11:32:52 -08:00
ia32	[IA64] ia32 nopage	2007-12-18 16:55:46 -08:00
kernel	[IA64] Adjust CMCI mask on CPU hotplug	2007-12-19 12:30:47 -08:00
lib	[IA64] export copy_page() to modules	2007-12-07 16:10:19 -08:00
mm	[IA64] Avoid unnecessary TLB flushes when allocating memory	2007-12-18 16:56:50 -08:00
oprofile	Combine instrumentation menus in kernel/Kconfig.instrumentation	2007-10-19 11:53:54 -07:00
pci	[IA64] Nail two more simple section mismatch errors	2007-07-25 13:08:41 -07:00
scripts	[IA64] don't assume that unwcheck.py is executable	2007-12-07 14:42:08 -08:00
sn	[IA64] Update Altix nofault code	2008-01-03 13:22:54 -08:00
Kconfig	typo fixes	2007-10-20 01:34:40 +02:00
Kconfig.debug	…
Makefile	[IA64] don't assume that unwcheck.py is executable	2007-12-07 14:42:08 -08:00
defconfig	[IA64] Update arch/ia64/configs/* s/SLAB/SLUB/	2007-08-13 14:54:34 -07:00
install.sh	…
module.lds	…