b5680e0b59
This patch is to add mx28 dual fec support. Here are some key notes for mx28 fec controller. - The mx28 fec controller naming ENET-MAC is a different IP from FEC used on other i.mx variants. But they are basically compatible on software interface, so it's possible to share the same driver. - ENET-MAC design on mx28 made an improper assumption that it runs on a big-endian system. As the result, driver has to swap every frame going to and coming from the controller. - The external phys can only be configured by fec0, which means fec1 can not work independently and both phys need to be configured by mii_bus attached on fec0. - ENET-MAC reset will get mac address registers reset too. - ENET-MAC MII/RMII mode and 10M/100M speed are configured differently FEC. - ETHER_EN bit must be set to get ENET-MAC interrupt work. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
149 lines
6.5 KiB
C
149 lines
6.5 KiB
C
/****************************************************************************/
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/*
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* fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
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* processors.
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*
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* (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000-2001, Lineo (www.lineo.com)
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*/
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/****************************************************************************/
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#ifndef FEC_H
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#define FEC_H
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/****************************************************************************/
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
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defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
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/*
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* Just figures, Motorola would have to change the offsets for
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* registers in the same peripheral device on different models
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* of the ColdFire!
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*/
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#define FEC_IEVENT 0x004 /* Interrupt event reg */
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#define FEC_IMASK 0x008 /* Interrupt mask reg */
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#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
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#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
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#define FEC_ECNTRL 0x024 /* Ethernet control reg */
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#define FEC_MII_DATA 0x040 /* MII manage frame reg */
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#define FEC_MII_SPEED 0x044 /* MII speed control reg */
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#define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
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#define FEC_R_CNTRL 0x084 /* Receive control reg */
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#define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
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#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
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#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
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#define FEC_OPD 0x0ec /* Opcode + Pause duration */
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#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
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#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
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#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
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#define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */
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#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
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#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
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#define FEC_R_FSTART 0x150 /* FIFO receive start reg */
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#define FEC_R_DES_START 0x180 /* Receive descriptor ring */
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#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
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#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
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#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
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#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
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#else
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#define FEC_ECNTRL 0x000 /* Ethernet control reg */
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#define FEC_IEVENT 0x004 /* Interrupt even reg */
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#define FEC_IMASK 0x008 /* Interrupt mask reg */
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#define FEC_IVEC 0x00c /* Interrupt vec status reg */
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#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
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#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
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#define FEC_MII_DATA 0x040 /* MII manage frame reg */
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#define FEC_MII_SPEED 0x044 /* MII speed control reg */
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#define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
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#define FEC_R_FSTART 0x090 /* FIFO receive start reg */
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#define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */
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#define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
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#define FEC_R_CNTRL 0x104 /* Receive control reg */
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#define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
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#define FEC_X_CNTRL 0x144 /* Transmit Control reg */
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#define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */
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#define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
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#define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
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#define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
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#define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */
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#define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */
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#define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */
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#define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
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#endif /* CONFIG_M5272 */
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/*
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* Define the buffer descriptor structure.
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*/
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#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
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struct bufdesc {
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unsigned short cbd_datlen; /* Data length */
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unsigned short cbd_sc; /* Control and status info */
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unsigned long cbd_bufaddr; /* Buffer address */
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};
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#else
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struct bufdesc {
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unsigned short cbd_sc; /* Control and status info */
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unsigned short cbd_datlen; /* Data length */
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unsigned long cbd_bufaddr; /* Buffer address */
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};
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#endif
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/*
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* The following definitions courtesy of commproc.h, which where
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* Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
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*/
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#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
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#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
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#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
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#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
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#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
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#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
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#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
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#define BD_SC_BR ((ushort)0x0020) /* Break received */
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#define BD_SC_FR ((ushort)0x0010) /* Framing error */
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#define BD_SC_PR ((ushort)0x0008) /* Parity error */
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#define BD_SC_OV ((ushort)0x0002) /* Overrun */
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#define BD_SC_CD ((ushort)0x0001) /* ?? */
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/* Buffer descriptor control/status used by Ethernet receive.
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*/
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#define BD_ENET_RX_EMPTY ((ushort)0x8000)
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#define BD_ENET_RX_WRAP ((ushort)0x2000)
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#define BD_ENET_RX_INTR ((ushort)0x1000)
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#define BD_ENET_RX_LAST ((ushort)0x0800)
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#define BD_ENET_RX_FIRST ((ushort)0x0400)
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#define BD_ENET_RX_MISS ((ushort)0x0100)
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#define BD_ENET_RX_LG ((ushort)0x0020)
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#define BD_ENET_RX_NO ((ushort)0x0010)
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#define BD_ENET_RX_SH ((ushort)0x0008)
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#define BD_ENET_RX_CR ((ushort)0x0004)
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#define BD_ENET_RX_OV ((ushort)0x0002)
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#define BD_ENET_RX_CL ((ushort)0x0001)
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#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
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/* Buffer descriptor control/status used by Ethernet transmit.
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*/
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#define BD_ENET_TX_READY ((ushort)0x8000)
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#define BD_ENET_TX_PAD ((ushort)0x4000)
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#define BD_ENET_TX_WRAP ((ushort)0x2000)
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#define BD_ENET_TX_INTR ((ushort)0x1000)
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#define BD_ENET_TX_LAST ((ushort)0x0800)
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#define BD_ENET_TX_TC ((ushort)0x0400)
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#define BD_ENET_TX_DEF ((ushort)0x0200)
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#define BD_ENET_TX_HB ((ushort)0x0100)
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#define BD_ENET_TX_LC ((ushort)0x0080)
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#define BD_ENET_TX_RL ((ushort)0x0040)
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#define BD_ENET_TX_RCMASK ((ushort)0x003c)
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#define BD_ENET_TX_UN ((ushort)0x0002)
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#define BD_ENET_TX_CSL ((ushort)0x0001)
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#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
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/****************************************************************************/
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#endif /* FEC_H */
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