481 lines
11 KiB
C
481 lines
11 KiB
C
/*
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* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - Power Management support
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*
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* Based on arch/arm/mach-s3c2410/pm.c
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/syscore_ops.h>
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#include <linux/cpu_pm.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <plat/pm-common.h>
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#include <plat/pll.h>
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#include <plat/regs-srom.h>
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#include <mach/map.h>
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#include "common.h"
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#include "regs-pmu.h"
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/**
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* struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
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* @hwirq: Hardware IRQ signal of the GIC
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* @mask: Mask in PMU wake-up mask register
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*/
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struct exynos_wkup_irq {
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unsigned int hwirq;
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u32 mask;
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};
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static struct sleep_save exynos5_sys_save[] = {
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SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
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};
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static struct sleep_save exynos_core_save[] = {
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/* SROM side */
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SAVE_ITEM(S5P_SROM_BW),
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SAVE_ITEM(S5P_SROM_BC0),
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SAVE_ITEM(S5P_SROM_BC1),
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SAVE_ITEM(S5P_SROM_BC2),
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SAVE_ITEM(S5P_SROM_BC3),
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};
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/*
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* GIC wake-up support
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*/
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static u32 exynos_irqwake_intmask = 0xffffffff;
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static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
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{ 76, BIT(1) }, /* RTC alarm */
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{ 77, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
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{ 75, BIT(1) }, /* RTC alarm */
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{ 76, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
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{
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const struct exynos_wkup_irq *wkup_irq;
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if (soc_is_exynos5250())
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wkup_irq = exynos5250_wkup_irq;
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else
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wkup_irq = exynos4_wkup_irq;
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while (wkup_irq->mask) {
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if (wkup_irq->hwirq == data->hwirq) {
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if (!state)
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exynos_irqwake_intmask |= wkup_irq->mask;
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else
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exynos_irqwake_intmask &= ~wkup_irq->mask;
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return 0;
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}
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++wkup_irq;
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}
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return -ENOENT;
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}
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/**
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* exynos_core_power_down : power down the specified cpu
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* @cpu : the cpu to power down
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*
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* Power down the specified cpu. The sequence must be finished by a
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* call to cpu_do_idle()
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*
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*/
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void exynos_cpu_power_down(int cpu)
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{
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__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
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}
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/**
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* exynos_cpu_power_up : power up the specified cpu
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* @cpu : the cpu to power up
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*
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* Power up the specified cpu
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*/
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void exynos_cpu_power_up(int cpu)
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{
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__raw_writel(S5P_CORE_LOCAL_PWR_EN,
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EXYNOS_ARM_CORE_CONFIGURATION(cpu));
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}
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/**
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* exynos_cpu_power_state : returns the power state of the cpu
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* @cpu : the cpu to retrieve the power state from
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*
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*/
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int exynos_cpu_power_state(int cpu)
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{
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return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
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S5P_CORE_LOCAL_PWR_EN);
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}
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/**
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* exynos_cluster_power_down : power down the specified cluster
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* @cluster : the cluster to power down
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*/
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void exynos_cluster_power_down(int cluster)
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{
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__raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
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}
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/**
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* exynos_cluster_power_up : power up the specified cluster
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* @cluster : the cluster to power up
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*/
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void exynos_cluster_power_up(int cluster)
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{
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__raw_writel(S5P_CORE_LOCAL_PWR_EN,
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EXYNOS_COMMON_CONFIGURATION(cluster));
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}
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/**
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* exynos_cluster_power_state : returns the power state of the cluster
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* @cluster : the cluster to retrieve the power state from
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*
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*/
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int exynos_cluster_power_state(int cluster)
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{
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return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
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S5P_CORE_LOCAL_PWR_EN);
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}
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#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
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S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
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(sysram_base_addr + 0x24) : S5P_INFORM0))
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#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
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S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
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(sysram_base_addr + 0x20) : S5P_INFORM1))
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#define S5P_CHECK_AFTR 0xFCBA0D10
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#define S5P_CHECK_SLEEP 0x00000BAD
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/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
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static void exynos_set_wakeupmask(long mask)
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{
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__raw_writel(mask, S5P_WAKEUP_MASK);
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}
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static void exynos_cpu_set_boot_vector(long flags)
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{
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__raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
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__raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
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}
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void exynos_enter_aftr(void)
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{
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exynos_set_wakeupmask(0x0000ff3e);
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exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
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/* Set value of power down register for aftr mode */
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exynos_sys_powerdown_conf(SYS_AFTR);
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}
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/* For Cortex-A9 Diagnostic and Power control register */
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static unsigned int save_arm_register[2];
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static void exynos_cpu_save_register(void)
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{
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unsigned long tmp;
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/* Save Power control register */
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asm ("mrc p15, 0, %0, c15, c0, 0"
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: "=r" (tmp) : : "cc");
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save_arm_register[0] = tmp;
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/* Save Diagnostic register */
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asm ("mrc p15, 0, %0, c15, c0, 1"
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: "=r" (tmp) : : "cc");
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save_arm_register[1] = tmp;
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}
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static void exynos_cpu_restore_register(void)
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{
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unsigned long tmp;
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/* Restore Power control register */
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tmp = save_arm_register[0];
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asm volatile ("mcr p15, 0, %0, c15, c0, 0"
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: : "r" (tmp)
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: "cc");
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/* Restore Diagnostic register */
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tmp = save_arm_register[1];
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asm volatile ("mcr p15, 0, %0, c15, c0, 1"
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: : "r" (tmp)
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: "cc");
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}
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static int exynos_cpu_suspend(unsigned long arg)
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{
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#ifdef CONFIG_CACHE_L2X0
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outer_flush_all();
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#endif
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if (soc_is_exynos5250())
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flush_cache_all();
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/* issue the standby signal into the pm unit. */
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cpu_do_idle();
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pr_info("Failed to suspend the system\n");
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return 1; /* Aborting suspend */
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}
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static void exynos_pm_prepare(void)
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{
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unsigned int tmp;
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/* Set wake-up mask registers */
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__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
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__raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
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s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (soc_is_exynos5250()) {
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s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
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/* Disable USE_RETENTION of JPEG_MEM_OPTION */
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tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
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tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
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__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
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}
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/* Set value of power down register for sleep mode */
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exynos_sys_powerdown_conf(SYS_SLEEP);
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__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
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/* ensure at least INFORM0 has the resume address */
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__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
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}
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static void exynos_pm_central_suspend(void)
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{
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unsigned long tmp;
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/* Setting Central Sequence Register for power down mode */
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tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
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__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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}
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static int exynos_pm_suspend(void)
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{
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unsigned long tmp;
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exynos_pm_central_suspend();
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/* Setting SEQ_OPTION register */
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tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
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__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
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if (!soc_is_exynos5250())
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exynos_cpu_save_register();
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return 0;
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}
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static int exynos_pm_central_resume(void)
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{
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unsigned long tmp;
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/*
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* If PMU failed while entering sleep mode, WFI will be
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* ignored by PMU and then exiting cpu_do_idle().
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* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
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* in this situation.
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*/
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tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
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tmp |= S5P_CENTRAL_LOWPWR_CFG;
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__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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/* clear the wakeup state register */
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__raw_writel(0x0, S5P_WAKEUP_STAT);
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/* No need to perform below restore code */
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return -1;
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}
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return 0;
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}
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static void exynos_pm_resume(void)
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{
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if (exynos_pm_central_resume())
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goto early_wakeup;
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if (!soc_is_exynos5250())
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exynos_cpu_restore_register();
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/* For release retention */
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__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
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__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
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if (soc_is_exynos5250())
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s3c_pm_do_restore(exynos5_sys_save,
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ARRAY_SIZE(exynos5_sys_save));
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s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (!soc_is_exynos5250())
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scu_enable(S5P_VA_SCU);
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early_wakeup:
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/* Clear SLEEP mode set in INFORM1 */
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__raw_writel(0x0, S5P_INFORM1);
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return;
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}
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static struct syscore_ops exynos_pm_syscore_ops = {
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.suspend = exynos_pm_suspend,
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.resume = exynos_pm_resume,
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};
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/*
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* Suspend Ops
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*/
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static int exynos_suspend_enter(suspend_state_t state)
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{
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int ret;
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s3c_pm_debug_init();
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S3C_PMDBG("%s: suspending the system...\n", __func__);
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S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
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exynos_irqwake_intmask, exynos_get_eint_wake_mask());
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if (exynos_irqwake_intmask == -1U
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&& exynos_get_eint_wake_mask() == -1U) {
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pr_err("%s: No wake-up sources!\n", __func__);
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pr_err("%s: Aborting sleep\n", __func__);
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return -EINVAL;
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}
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s3c_pm_save_uarts();
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exynos_pm_prepare();
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flush_cache_all();
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s3c_pm_check_store();
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ret = cpu_suspend(0, exynos_cpu_suspend);
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if (ret)
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return ret;
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s3c_pm_restore_uarts();
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S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
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__raw_readl(S5P_WAKEUP_STAT));
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s3c_pm_check_restore();
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S3C_PMDBG("%s: resuming the system...\n", __func__);
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return 0;
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}
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static int exynos_suspend_prepare(void)
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{
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s3c_pm_check_prepare();
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return 0;
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}
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static void exynos_suspend_finish(void)
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{
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s3c_pm_check_cleanup();
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}
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static const struct platform_suspend_ops exynos_suspend_ops = {
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.enter = exynos_suspend_enter,
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.prepare = exynos_suspend_prepare,
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.finish = exynos_suspend_finish,
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.valid = suspend_valid_only_mem,
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};
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static int exynos_cpu_pm_notifier(struct notifier_block *self,
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unsigned long cmd, void *v)
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{
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int cpu = smp_processor_id();
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switch (cmd) {
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case CPU_PM_ENTER:
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if (cpu == 0) {
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exynos_pm_central_suspend();
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exynos_cpu_save_register();
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}
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break;
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case CPU_PM_EXIT:
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if (cpu == 0) {
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if (!soc_is_exynos5250())
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scu_enable(S5P_VA_SCU);
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exynos_cpu_restore_register();
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exynos_pm_central_resume();
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}
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block exynos_cpu_pm_notifier_block = {
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.notifier_call = exynos_cpu_pm_notifier,
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};
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void __init exynos_pm_init(void)
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{
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u32 tmp;
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cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
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/* Platform-specific GIC callback */
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gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
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/* All wakeup disable */
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tmp = __raw_readl(S5P_WAKEUP_MASK);
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tmp |= ((0xFF << 8) | (0x1F << 1));
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__raw_writel(tmp, S5P_WAKEUP_MASK);
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register_syscore_ops(&exynos_pm_syscore_ops);
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suspend_set_ops(&exynos_suspend_ops);
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}
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