linux/drivers/clk
Ryan Chen 046615ffd4 clk: aspeed: Fix APLL calculate formula from ast2600-A2
[ Upstream commit 6286ce1e3ece54799f12775f8ce2a1cba9cbcfc5 ]

Starting from A2, the A-PLL calculation has changed. Use the
existing formula for A0/A1 and the new formula for A2 onwards.

Fixes: d3d04f6c33 ("clk: Add support for AST2600 SoC")
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Link: https://lore.kernel.org/r/20210119061715.6043-1-ryan_chen@aspeedtech.com
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-03-04 10:26:34 +01:00
..
actions clk: actions: Fix h_clk for Actions S500 SoC 2020-08-21 13:05:33 +02:00
analogbits
at91 clk: at91: sam9x60: remove atmel,osc-bypass support 2020-12-30 11:51:29 +01:00
axis
axs10x
bcm clk: bcm2835: add missing release if devm_clk_hw_register fails 2020-10-29 09:57:55 +01:00
berlin
davinci clk: davinci: Use the correct size when allocating memory 2020-09-23 12:40:38 +02:00
h8300
hisilicon
imgtec
imx clk: imx8mq: Fix usdhc parents order 2020-10-29 09:57:56 +01:00
ingenic clk: ingenic: Fix divider calculation with div tables 2020-12-30 11:51:45 +01:00
keystone clk: keystone: sci-clk: fix parsing assigned-clock data during probe 2020-10-29 09:57:54 +01:00
loongson1
mediatek clk: mediatek: add UART0 clock support 2020-10-29 09:57:54 +01:00
meson clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() 2021-03-04 10:26:26 +01:00
microchip
mmp clk: mmp2: Fix the order of timer mux parents 2020-02-05 21:22:43 +00:00
mvebu clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 2020-12-30 11:51:45 +01:00
mxs
nxp
pistachio
pxa clk: pxa: fix one of the pxa RTC clocks 2020-01-04 19:18:11 +01:00
qcom clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs 2021-03-04 10:26:33 +01:00
renesas clk: renesas: r9a06g032: Drop __packed for portability 2020-12-30 11:50:53 +01:00
rockchip clk: rockchip: Initialize hw to error to avoid undefined behavior 2020-10-29 09:57:54 +01:00
samsung clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSED 2020-10-07 08:01:28 +02:00
sifive clk: sifive: allocate sufficient memory for struct __prci_data 2020-06-30 15:37:01 -04:00
sirf clk: clk-atlas6: fix return value check in atlas6_clk_init() 2020-08-21 13:05:34 +02:00
socfpga clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk 2020-10-07 08:01:24 +02:00
spear
sprd clk: sprd: return correct type of value for _sprd_pll_recalc_rate 2020-06-24 17:50:35 +02:00
st clk: clk-flexgen: fix clock-critical handling 2020-06-24 17:50:17 +02:00
sunxi clk: sunxi: Fix incorrect usage of round_down() 2020-06-24 17:50:08 +02:00
sunxi-ng clk: sunxi-ng: h6: Fix clock divider range on some clocks 2021-03-04 10:26:29 +01:00
tegra clk: tegra30: Add hda clock default rates to clock driver 2021-01-27 11:47:44 +01:00
ti clk: ti: Fix memleak in ti_fapll_synth_setup 2020-12-30 11:51:28 +01:00
uniphier clk: uniphier: Add SCSSI clock gate for each channel 2020-02-24 08:36:42 +01:00
ux500
versatile
x86
zte
zynq
zynqmp clk: zynqmp: fix memory leak in zynqmp_register_clocks 2020-06-24 17:50:16 +02:00
Kconfig
Makefile
clk-asm9260.c
clk-aspeed.c
clk-aspeed.h
clk-ast2600.c clk: aspeed: Fix APLL calculate formula from ast2600-A2 2021-03-04 10:26:34 +01:00
clk-axi-clkgen.c
clk-axm5516.c
clk-bd718x7.c
clk-bulk.c
clk-cdce706.c
clk-cdce925.c
clk-clps711x.c
clk-composite.c
clk-conf.c
clk-cs2000-cp.c
clk-devres.c
clk-divider.c
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-mmio.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-gate.c
clk-gemini.c
clk-gpio.c clk: clk-gpio: propagate rate change to parent 2020-01-04 19:17:21 +01:00
clk-hi655x.c
clk-highbank.c
clk-hsdk-pll.c
clk-lochnagar.c
clk-max9485.c
clk-max77686.c
clk-milbeaut.c
clk-moxart.c
clk-multiplier.c
clk-mux.c
clk-nomadik.c
clk-npcm7xx.c
clk-nspire.c
clk-oxnas.c
clk-palmas.c
clk-pwm.c
clk-qoriq.c
clk-rk808.c
clk-s2mps11.c clk: s2mps11: Fix a resource leak in error handling paths in the probe function 2020-12-30 11:51:29 +01:00
clk-scmi.c clk: scmi: Fix min and max rate when registering clocks with discrete rates 2020-08-19 08:15:55 +02:00
clk-scpi.c
clk-si514.c
clk-si544.c
clk-si570.c
clk-si5341.c
clk-si5351.c
clk-si5351.h
clk-stm32f4.c
clk-stm32h7.c
clk-stm32mp1.c
clk-tango4.c
clk-twl6040.c
clk-u300.c
clk-versaclock5.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c PM: runtime: clk: Fix clk_pm_runtime_get() error path 2020-06-17 16:40:30 +02:00
clk.h
clkdev.c