460 lines
11 KiB
C
460 lines
11 KiB
C
/*
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* sh7372 Power management support
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*
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* Copyright (C) 2011 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/cpuidle.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/pm_clock.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/bitrev.h>
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#include <linux/console.h>
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#include <asm/io.h>
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#include <asm/tlbflush.h>
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#include <asm/suspend.h>
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#include <mach/common.h>
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#include <mach/sh7372.h>
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#include <mach/pm-rmobile.h>
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/* DBG */
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#define DBGREG1 0xe6100020
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#define DBGREG9 0xe6100040
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/* CPGA */
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#define SYSTBCR 0xe6150024
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#define MSTPSR0 0xe6150030
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#define MSTPSR1 0xe6150038
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#define MSTPSR2 0xe6150040
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#define MSTPSR3 0xe6150048
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#define MSTPSR4 0xe615004c
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#define PLLC01STPCR 0xe61500c8
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/* SYSC */
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#define SBAR 0xe6180020
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#define WUPRMSK 0xe6180028
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#define WUPSMSK 0xe618002c
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#define WUPSMSK2 0xe6180048
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#define WUPSFAC 0xe6180098
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#define IRQCR 0xe618022c
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#define IRQCR2 0xe6180238
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#define IRQCR3 0xe6180244
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#define IRQCR4 0xe6180248
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#define PDNSEL 0xe6180254
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/* INTC */
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#define ICR1A 0xe6900000
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#define ICR2A 0xe6900004
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#define ICR3A 0xe6900008
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#define ICR4A 0xe690000c
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#define INTMSK00A 0xe6900040
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#define INTMSK10A 0xe6900044
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#define INTMSK20A 0xe6900048
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#define INTMSK30A 0xe690004c
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/* MFIS */
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#define SMFRAM 0xe6a70000
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/* AP-System Core */
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#define APARMBAREA 0xe6f10020
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#ifdef CONFIG_PM
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struct rmobile_pm_domain sh7372_pd_a4lc = {
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.genpd.name = "A4LC",
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.bit_shift = 1,
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};
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struct rmobile_pm_domain sh7372_pd_a4mp = {
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.genpd.name = "A4MP",
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.bit_shift = 2,
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};
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struct rmobile_pm_domain sh7372_pd_d4 = {
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.genpd.name = "D4",
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.bit_shift = 3,
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};
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static int sh7372_a4r_pd_suspend(void)
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{
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sh7372_intcs_suspend();
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__raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
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return 0;
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}
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struct rmobile_pm_domain sh7372_pd_a4r = {
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.genpd.name = "A4R",
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.bit_shift = 5,
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.suspend = sh7372_a4r_pd_suspend,
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.resume = sh7372_intcs_resume,
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};
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struct rmobile_pm_domain sh7372_pd_a3rv = {
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.genpd.name = "A3RV",
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.bit_shift = 6,
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};
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struct rmobile_pm_domain sh7372_pd_a3ri = {
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.genpd.name = "A3RI",
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.bit_shift = 8,
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};
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static int sh7372_pd_a4s_suspend(void)
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{
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/*
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* The A4S domain contains the CPU core and therefore it should
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* only be turned off if the CPU is in use.
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*/
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return -EBUSY;
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}
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struct rmobile_pm_domain sh7372_pd_a4s = {
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.genpd.name = "A4S",
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.bit_shift = 10,
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.gov = &pm_domain_always_on_gov,
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.no_debug = true,
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.suspend = sh7372_pd_a4s_suspend,
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};
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static int sh7372_a3sp_pd_suspend(void)
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{
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/*
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* Serial consoles make use of SCIF hardware located in A3SP,
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* keep such power domain on if "no_console_suspend" is set.
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*/
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return console_suspend_enabled ? 0 : -EBUSY;
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}
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struct rmobile_pm_domain sh7372_pd_a3sp = {
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.genpd.name = "A3SP",
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.bit_shift = 11,
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.gov = &pm_domain_always_on_gov,
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.no_debug = true,
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.suspend = sh7372_a3sp_pd_suspend,
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};
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struct rmobile_pm_domain sh7372_pd_a3sg = {
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.genpd.name = "A3SG",
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.bit_shift = 13,
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};
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#endif /* CONFIG_PM */
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#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
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static void sh7372_set_reset_vector(unsigned long address)
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{
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/* set reset vector, translate 4k */
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__raw_writel(address, SBAR);
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__raw_writel(0, APARMBAREA);
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}
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static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
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{
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if (pllc0_on)
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__raw_writel(0, PLLC01STPCR);
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else
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__raw_writel(1 << 28, PLLC01STPCR);
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__raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
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cpu_suspend(sleep_mode, sh7372_do_idle_sysc);
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__raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
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/* disable reset vector translation */
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__raw_writel(0, SBAR);
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}
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static int sh7372_sysc_valid(unsigned long *mskp, unsigned long *msk2p)
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{
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unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
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unsigned long msk, msk2;
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/* check active clocks to determine potential wakeup sources */
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mstpsr0 = __raw_readl(MSTPSR0);
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if ((mstpsr0 & 0x00000003) != 0x00000003) {
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pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
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return 0;
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}
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mstpsr1 = __raw_readl(MSTPSR1);
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if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
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pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
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return 0;
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}
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mstpsr2 = __raw_readl(MSTPSR2);
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if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
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pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
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return 0;
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}
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mstpsr3 = __raw_readl(MSTPSR3);
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if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
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pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
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return 0;
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}
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mstpsr4 = __raw_readl(MSTPSR4);
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if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
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pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
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return 0;
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}
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msk = 0;
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msk2 = 0;
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/* make bitmaps of limited number of wakeup sources */
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if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
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msk |= 1 << 31;
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if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
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msk |= 1 << 21;
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if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
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msk |= 1 << 2;
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if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
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msk |= 1 << 1;
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if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
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msk |= 1 << 1;
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if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
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msk |= 1 << 1;
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if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
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msk2 |= 1 << 17;
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*mskp = msk;
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*msk2p = msk2;
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return 1;
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}
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static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
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{
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u16 tmp, irqcr1, irqcr2;
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int k;
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irqcr1 = 0;
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irqcr2 = 0;
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/* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
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for (k = 0; k <= 7; k++) {
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tmp = (icr >> ((7 - k) * 4)) & 0xf;
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irqcr1 |= (tmp & 0x03) << (k * 2);
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irqcr2 |= (tmp >> 2) << (k * 2);
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}
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*irqcr1p = irqcr1;
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*irqcr2p = irqcr2;
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}
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static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
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{
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u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
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unsigned long tmp;
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/* read IRQ0A -> IRQ15A mask */
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tmp = bitrev8(__raw_readb(INTMSK00A));
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tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
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/* setup WUPSMSK from clocks and external IRQ mask */
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msk = (~msk & 0xc030000f) | (tmp << 4);
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__raw_writel(msk, WUPSMSK);
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/* propage level/edge trigger for external IRQ 0->15 */
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sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
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sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
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__raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
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__raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
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/* read IRQ16A -> IRQ31A mask */
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tmp = bitrev8(__raw_readb(INTMSK20A));
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tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
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/* setup WUPSMSK2 from clocks and external IRQ mask */
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msk2 = (~msk2 & 0x00030000) | tmp;
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__raw_writel(msk2, WUPSMSK2);
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/* propage level/edge trigger for external IRQ 16->31 */
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sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
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sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
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__raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
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__raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
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}
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static void sh7372_enter_a3sm_common(int pllc0_on)
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{
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/* use INTCA together with SYSC for wakeup */
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sh7372_setup_sysc(1 << 0, 0);
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sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
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sh7372_enter_sysc(pllc0_on, 1 << 12);
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}
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#endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
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#ifdef CONFIG_CPU_IDLE
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static int sh7372_do_idle_core_standby(unsigned long unused)
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{
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cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
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return 0;
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}
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static void sh7372_enter_core_standby(void)
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{
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sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
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/* enter sleep mode with SYSTBCR to 0x10 */
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__raw_writel(0x10, SYSTBCR);
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cpu_suspend(0, sh7372_do_idle_core_standby);
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__raw_writel(0, SYSTBCR);
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/* disable reset vector translation */
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__raw_writel(0, SBAR);
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}
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static void sh7372_enter_a3sm_pll_on(void)
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{
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sh7372_enter_a3sm_common(1);
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}
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static void sh7372_enter_a3sm_pll_off(void)
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{
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sh7372_enter_a3sm_common(0);
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}
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static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
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{
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struct cpuidle_state *state = &drv->states[drv->state_count];
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snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
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strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
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state->exit_latency = 10;
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state->target_residency = 20 + 10;
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state->flags = CPUIDLE_FLAG_TIME_VALID;
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shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
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drv->state_count++;
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state = &drv->states[drv->state_count];
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snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
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strncpy(state->desc, "A3SM PLL ON", CPUIDLE_DESC_LEN);
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state->exit_latency = 20;
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state->target_residency = 30 + 20;
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state->flags = CPUIDLE_FLAG_TIME_VALID;
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shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_on;
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drv->state_count++;
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state = &drv->states[drv->state_count];
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snprintf(state->name, CPUIDLE_NAME_LEN, "C4");
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strncpy(state->desc, "A3SM PLL OFF", CPUIDLE_DESC_LEN);
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state->exit_latency = 120;
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state->target_residency = 30 + 120;
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state->flags = CPUIDLE_FLAG_TIME_VALID;
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shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_off;
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drv->state_count++;
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}
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static void sh7372_cpuidle_init(void)
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{
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shmobile_cpuidle_setup = sh7372_cpuidle_setup;
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}
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#else
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static void sh7372_cpuidle_init(void) {}
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#endif
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#ifdef CONFIG_SUSPEND
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static void sh7372_enter_a4s_common(int pllc0_on)
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{
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sh7372_intca_suspend();
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memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
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sh7372_set_reset_vector(SMFRAM);
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sh7372_enter_sysc(pllc0_on, 1 << 10);
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sh7372_intca_resume();
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}
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static int sh7372_enter_suspend(suspend_state_t suspend_state)
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{
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unsigned long msk, msk2;
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/* check active clocks to determine potential wakeup sources */
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if (sh7372_sysc_valid(&msk, &msk2)) {
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if (!console_suspend_enabled &&
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sh7372_pd_a4s.genpd.status == GPD_STATE_POWER_OFF) {
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/* convert INTC mask/sense to SYSC mask/sense */
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sh7372_setup_sysc(msk, msk2);
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/* enter A4S sleep with PLLC0 off */
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pr_debug("entering A4S\n");
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sh7372_enter_a4s_common(0);
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return 0;
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}
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}
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/* default to enter A3SM sleep with PLLC0 off */
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pr_debug("entering A3SM\n");
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sh7372_enter_a3sm_common(0);
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return 0;
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}
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/**
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* sh7372_pm_notifier_fn - SH7372 PM notifier routine.
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* @notifier: Unused.
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* @pm_event: Event being handled.
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* @unused: Unused.
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*/
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static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
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unsigned long pm_event, void *unused)
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{
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switch (pm_event) {
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case PM_SUSPEND_PREPARE:
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/*
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* This is necessary, because the A4R domain has to be "on"
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* when suspend_device_irqs() and resume_device_irqs() are
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* executed during system suspend and resume, respectively, so
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* that those functions don't crash while accessing the INTCS.
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*/
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pm_genpd_poweron(&sh7372_pd_a4r.genpd);
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break;
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case PM_POST_SUSPEND:
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pm_genpd_poweroff_unused();
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break;
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}
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return NOTIFY_DONE;
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}
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static void sh7372_suspend_init(void)
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{
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shmobile_suspend_ops.enter = sh7372_enter_suspend;
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pm_notifier(sh7372_pm_notifier_fn, 0);
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}
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#else
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static void sh7372_suspend_init(void) {}
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#endif
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void __init sh7372_pm_init(void)
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{
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/* enable DBG hardware block to kick SYSC */
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__raw_writel(0x0000a500, DBGREG9);
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__raw_writel(0x0000a501, DBGREG9);
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__raw_writel(0x00000000, DBGREG1);
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/* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
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__raw_writel(0, PDNSEL);
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sh7372_suspend_init();
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sh7372_cpuidle_init();
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}
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