4d295db0ef
Adding support for BCM8727 - a dual port SFP+ PHY. That includes verification of the optic module vendor and part number - the list of approved modules resides on the nvram and the module is verified by the FW. Since not all users would like to use this verification feature, it can be disabled. The default behavior is to issue a warning if the module is not approved, but still allow using it - but it is also possible to disable the link if the module is not approved. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
195 lines
6.4 KiB
C
195 lines
6.4 KiB
C
/* Copyright 2008-2009 Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available
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* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*
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* Written by Yaniv Rosner
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*
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*/
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#ifndef BNX2X_LINK_H
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#define BNX2X_LINK_H
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/***********************************************************/
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/* Defines */
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/***********************************************************/
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#define DEFAULT_PHY_DEV_ADDR 3
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#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
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#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
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#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
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#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
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#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
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#define SPEED_AUTO_NEG 0
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#define SPEED_12000 12000
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#define SPEED_12500 12500
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#define SPEED_13000 13000
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#define SPEED_15000 15000
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#define SPEED_16000 16000
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#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
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#define SFP_EEPROM_VENDOR_NAME_SIZE 16
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#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
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#define SFP_EEPROM_VENDOR_OUI_SIZE 3
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#define SFP_EEPROM_PART_NO_ADDR 0x28
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#define SFP_EEPROM_PART_NO_SIZE 16
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#define PWR_FLT_ERR_MSG_LEN 250
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/***********************************************************/
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/* Structs */
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/***********************************************************/
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/* Inputs parameters to the CLC */
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struct link_params {
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u8 port;
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/* Default / User Configuration */
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u8 loopback_mode;
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#define LOOPBACK_NONE 0
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#define LOOPBACK_EMAC 1
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#define LOOPBACK_BMAC 2
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#define LOOPBACK_XGXS_10 3
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#define LOOPBACK_EXT_PHY 4
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#define LOOPBACK_EXT 5
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u16 req_duplex;
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u16 req_flow_ctrl;
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u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
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req_flow_ctrl is set to AUTO */
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u16 req_line_speed; /* Also determine AutoNeg */
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/* Device parameters */
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u8 mac_addr[6];
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/* shmem parameters */
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u32 shmem_base;
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u32 speed_cap_mask;
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u32 switch_cfg;
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#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
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#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
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#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
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u16 hw_led_mode; /* part of the hw_config read from the shmem */
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u32 lane_config;
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u32 ext_phy_config;
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#define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
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#define SERDES_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
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PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
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/* Phy register parameter */
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u32 chip_id;
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/* phy_addr populated by the CLC */
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u8 phy_addr;
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u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */
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u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */
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u32 feature_config_flags;
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#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
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#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
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#define FEATURE_CONFIG_BCM8727_NOC (1<<3)
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/* Device pointer passed to all callback functions */
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struct bnx2x *bp;
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};
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/* Output parameters */
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struct link_vars {
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u8 phy_link_up; /* internal phy link indication */
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u8 link_up;
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u16 duplex;
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u16 flow_ctrl;
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u32 ieee_fc;
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u8 mac_type;
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#define MAC_TYPE_NONE 0
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#define MAC_TYPE_EMAC 1
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#define MAC_TYPE_BMAC 2
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u16 line_speed;
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u32 autoneg;
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#define AUTO_NEG_DISABLED 0x0
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#define AUTO_NEG_ENABLED 0x1
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#define AUTO_NEG_COMPLETE 0x2
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#define AUTO_NEG_PARALLEL_DETECTION_USED 0x3
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u8 phy_flags;
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/* The same definitions as the shmem parameter */
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u32 link_status;
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};
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/***********************************************************/
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/* Functions */
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/***********************************************************/
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/* Initialize the phy */
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u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
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/* Reset the link. Should be called when driver or interface goes down
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Before calling phy firmware upgrade, the reset_ext_phy should be set
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to 0 */
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u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
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u8 reset_ext_phy);
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/* bnx2x_link_update should be called upon link interrupt */
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u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
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/* use the following cl45 functions to read/write from external_phy
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In order to use it to read/write internal phy registers, use
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DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
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Use ext_phy_type of 0 in case of cl22 over cl45
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the register */
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u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
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u8 phy_addr, u8 devad, u16 reg, u16 *ret_val);
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u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
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u8 phy_addr, u8 devad, u16 reg, u16 val);
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/* Reads the link_status from the shmem,
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and update the link vars accordingly */
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void bnx2x_link_status_update(struct link_params *input,
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struct link_vars *output);
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/* returns string representing the fw_version of the external phy */
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u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
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u8 *version, u16 len);
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/* Set/Unset the led
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Basically, the CLC takes care of the led for the link, but in case one needs
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to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
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blink the led, and LED_MODE_OFF to set the led off.*/
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u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
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u16 hw_led_mode, u32 chip_id);
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#define LED_MODE_OFF 0
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#define LED_MODE_OPER 2
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u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port, u32 led_idx, u32 value);
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u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
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u8 driver_loaded, char data[], u32 size);
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/* bnx2x_handle_module_detect_int should be called upon module detection
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interrupt */
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void bnx2x_handle_module_detect_int(struct link_params *params);
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/* Get the actual link status. In case it returns 0, link is up,
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otherwise link is down*/
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u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
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/* One-time initialization for external phy after power up */
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u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base);
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u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
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u8 byte_cnt, u8 *o_buf);
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#endif /* BNX2X_LINK_H */
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