383 lines
12 KiB
C
383 lines
12 KiB
C
/*
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* _tiomap.h
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*
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* DSP-BIOS Bridge driver support functions for TI OMAP processors.
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*
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* Definitions and types private to this Bridge driver.
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*
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* Copyright (C) 2005-2006 Texas Instruments, Inc.
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*
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* This package is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#ifndef _TIOMAP_
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#define _TIOMAP_
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/*
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* XXX These powerdomain.h/clockdomain.h includes are wrong and should
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* be removed. No driver should call pwrdm_* or clkdm_* functions
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* directly; they should rely on OMAP core code to do this.
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*/
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#include <mach-omap2/powerdomain.h>
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#include <mach-omap2/clockdomain.h>
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/*
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* XXX These mach-omap2/ includes are wrong and should be removed. No
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* driver should read or write to PRM/CM registers directly; they
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* should rely on OMAP core code to do this.
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*/
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#include <mach-omap2/cm2xxx_3xxx.h>
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#include <mach-omap2/prm-regbits-34xx.h>
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#include <mach-omap2/cm-regbits-34xx.h>
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#include <dspbridge/devdefs.h>
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#include <hw_defs.h>
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#include <dspbridge/dspioctl.h> /* for bridge_ioctl_extproc defn */
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#include <dspbridge/sync.h>
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#include <dspbridge/clk.h>
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struct map_l4_peripheral {
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u32 phys_addr;
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u32 dsp_virt_addr;
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};
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#define ARM_MAILBOX_START 0xfffcf000
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#define ARM_MAILBOX_LENGTH 0x800
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/* New Registers in OMAP3.1 */
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#define TESTBLOCK_ID_START 0xfffed400
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#define TESTBLOCK_ID_LENGTH 0xff
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/* ID Returned by OMAP1510 */
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#define TBC_ID_VALUE 0xB47002F
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#define SPACE_LENGTH 0x2000
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#define API_CLKM_DPLL_DMA 0xfffec000
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#define ARM_INTERRUPT_OFFSET 0xb00
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#define BIOS24XX
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#define L4_PERIPHERAL_NULL 0x0
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#define DSPVA_PERIPHERAL_NULL 0x0
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#define MAX_LOCK_TLB_ENTRIES 15
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#define L4_PERIPHERAL_PRM 0x48306000 /*PRM L4 Peripheral */
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#define DSPVA_PERIPHERAL_PRM 0x1181e000
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#define L4_PERIPHERAL_SCM 0x48002000 /*SCM L4 Peripheral */
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#define DSPVA_PERIPHERAL_SCM 0x1181f000
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#define L4_PERIPHERAL_MMU 0x5D000000 /*MMU L4 Peripheral */
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#define DSPVA_PERIPHERAL_MMU 0x11820000
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#define L4_PERIPHERAL_CM 0x48004000 /* Core L4, Clock Management */
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#define DSPVA_PERIPHERAL_CM 0x1181c000
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#define L4_PERIPHERAL_PER 0x48005000 /* PER */
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#define DSPVA_PERIPHERAL_PER 0x1181d000
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#define L4_PERIPHERAL_GPIO1 0x48310000
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#define DSPVA_PERIPHERAL_GPIO1 0x11809000
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#define L4_PERIPHERAL_GPIO2 0x49050000
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#define DSPVA_PERIPHERAL_GPIO2 0x1180a000
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#define L4_PERIPHERAL_GPIO3 0x49052000
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#define DSPVA_PERIPHERAL_GPIO3 0x1180b000
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#define L4_PERIPHERAL_GPIO4 0x49054000
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#define DSPVA_PERIPHERAL_GPIO4 0x1180c000
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#define L4_PERIPHERAL_GPIO5 0x49056000
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#define DSPVA_PERIPHERAL_GPIO5 0x1180d000
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#define L4_PERIPHERAL_IVA2WDT 0x49030000
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#define DSPVA_PERIPHERAL_IVA2WDT 0x1180e000
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#define L4_PERIPHERAL_DISPLAY 0x48050000
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#define DSPVA_PERIPHERAL_DISPLAY 0x1180f000
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#define L4_PERIPHERAL_SSI 0x48058000
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#define DSPVA_PERIPHERAL_SSI 0x11804000
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#define L4_PERIPHERAL_GDD 0x48059000
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#define DSPVA_PERIPHERAL_GDD 0x11805000
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#define L4_PERIPHERAL_SS1 0x4805a000
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#define DSPVA_PERIPHERAL_SS1 0x11806000
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#define L4_PERIPHERAL_SS2 0x4805b000
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#define DSPVA_PERIPHERAL_SS2 0x11807000
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#define L4_PERIPHERAL_CAMERA 0x480BC000
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#define DSPVA_PERIPHERAL_CAMERA 0x11819000
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#define L4_PERIPHERAL_SDMA 0x48056000
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#define DSPVA_PERIPHERAL_SDMA 0x11810000 /* 0x1181d000 conflict w/ PER */
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#define L4_PERIPHERAL_UART1 0x4806a000
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#define DSPVA_PERIPHERAL_UART1 0x11811000
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#define L4_PERIPHERAL_UART2 0x4806c000
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#define DSPVA_PERIPHERAL_UART2 0x11812000
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#define L4_PERIPHERAL_UART3 0x49020000
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#define DSPVA_PERIPHERAL_UART3 0x11813000
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#define L4_PERIPHERAL_MCBSP1 0x48074000
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#define DSPVA_PERIPHERAL_MCBSP1 0x11814000
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#define L4_PERIPHERAL_MCBSP2 0x49022000
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#define DSPVA_PERIPHERAL_MCBSP2 0x11815000
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#define L4_PERIPHERAL_MCBSP3 0x49024000
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#define DSPVA_PERIPHERAL_MCBSP3 0x11816000
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#define L4_PERIPHERAL_MCBSP4 0x49026000
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#define DSPVA_PERIPHERAL_MCBSP4 0x11817000
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#define L4_PERIPHERAL_MCBSP5 0x48096000
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#define DSPVA_PERIPHERAL_MCBSP5 0x11818000
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#define L4_PERIPHERAL_GPTIMER5 0x49038000
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#define DSPVA_PERIPHERAL_GPTIMER5 0x11800000
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#define L4_PERIPHERAL_GPTIMER6 0x4903a000
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#define DSPVA_PERIPHERAL_GPTIMER6 0x11801000
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#define L4_PERIPHERAL_GPTIMER7 0x4903c000
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#define DSPVA_PERIPHERAL_GPTIMER7 0x11802000
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#define L4_PERIPHERAL_GPTIMER8 0x4903e000
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#define DSPVA_PERIPHERAL_GPTIMER8 0x11803000
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#define L4_PERIPHERAL_SPI1 0x48098000
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#define DSPVA_PERIPHERAL_SPI1 0x1181a000
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#define L4_PERIPHERAL_SPI2 0x4809a000
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#define DSPVA_PERIPHERAL_SPI2 0x1181b000
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#define L4_PERIPHERAL_MBOX 0x48094000
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#define DSPVA_PERIPHERAL_MBOX 0x11808000
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#define PM_GRPSEL_BASE 0x48307000
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#define DSPVA_GRPSEL_BASE 0x11821000
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#define L4_PERIPHERAL_SIDETONE_MCBSP2 0x49028000
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#define DSPVA_PERIPHERAL_SIDETONE_MCBSP2 0x11824000
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#define L4_PERIPHERAL_SIDETONE_MCBSP3 0x4902a000
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#define DSPVA_PERIPHERAL_SIDETONE_MCBSP3 0x11825000
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/* define a static array with L4 mappings */
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static const struct map_l4_peripheral l4_peripheral_table[] = {
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{L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX},
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{L4_PERIPHERAL_SCM, DSPVA_PERIPHERAL_SCM},
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{L4_PERIPHERAL_MMU, DSPVA_PERIPHERAL_MMU},
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{L4_PERIPHERAL_GPTIMER5, DSPVA_PERIPHERAL_GPTIMER5},
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{L4_PERIPHERAL_GPTIMER6, DSPVA_PERIPHERAL_GPTIMER6},
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{L4_PERIPHERAL_GPTIMER7, DSPVA_PERIPHERAL_GPTIMER7},
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{L4_PERIPHERAL_GPTIMER8, DSPVA_PERIPHERAL_GPTIMER8},
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{L4_PERIPHERAL_GPIO1, DSPVA_PERIPHERAL_GPIO1},
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{L4_PERIPHERAL_GPIO2, DSPVA_PERIPHERAL_GPIO2},
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{L4_PERIPHERAL_GPIO3, DSPVA_PERIPHERAL_GPIO3},
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{L4_PERIPHERAL_GPIO4, DSPVA_PERIPHERAL_GPIO4},
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{L4_PERIPHERAL_GPIO5, DSPVA_PERIPHERAL_GPIO5},
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{L4_PERIPHERAL_IVA2WDT, DSPVA_PERIPHERAL_IVA2WDT},
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{L4_PERIPHERAL_DISPLAY, DSPVA_PERIPHERAL_DISPLAY},
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{L4_PERIPHERAL_SSI, DSPVA_PERIPHERAL_SSI},
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{L4_PERIPHERAL_GDD, DSPVA_PERIPHERAL_GDD},
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{L4_PERIPHERAL_SS1, DSPVA_PERIPHERAL_SS1},
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{L4_PERIPHERAL_SS2, DSPVA_PERIPHERAL_SS2},
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{L4_PERIPHERAL_UART1, DSPVA_PERIPHERAL_UART1},
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{L4_PERIPHERAL_UART2, DSPVA_PERIPHERAL_UART2},
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{L4_PERIPHERAL_UART3, DSPVA_PERIPHERAL_UART3},
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{L4_PERIPHERAL_MCBSP1, DSPVA_PERIPHERAL_MCBSP1},
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{L4_PERIPHERAL_MCBSP2, DSPVA_PERIPHERAL_MCBSP2},
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{L4_PERIPHERAL_MCBSP3, DSPVA_PERIPHERAL_MCBSP3},
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{L4_PERIPHERAL_MCBSP4, DSPVA_PERIPHERAL_MCBSP4},
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{L4_PERIPHERAL_MCBSP5, DSPVA_PERIPHERAL_MCBSP5},
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{L4_PERIPHERAL_CAMERA, DSPVA_PERIPHERAL_CAMERA},
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{L4_PERIPHERAL_SPI1, DSPVA_PERIPHERAL_SPI1},
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{L4_PERIPHERAL_SPI2, DSPVA_PERIPHERAL_SPI2},
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{L4_PERIPHERAL_PRM, DSPVA_PERIPHERAL_PRM},
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{L4_PERIPHERAL_CM, DSPVA_PERIPHERAL_CM},
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{L4_PERIPHERAL_PER, DSPVA_PERIPHERAL_PER},
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{PM_GRPSEL_BASE, DSPVA_GRPSEL_BASE},
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{L4_PERIPHERAL_SIDETONE_MCBSP2, DSPVA_PERIPHERAL_SIDETONE_MCBSP2},
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{L4_PERIPHERAL_SIDETONE_MCBSP3, DSPVA_PERIPHERAL_SIDETONE_MCBSP3},
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{L4_PERIPHERAL_NULL, DSPVA_PERIPHERAL_NULL}
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};
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/*
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* 15 10 0
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* ---------------------------------
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* |0|0|1|0|0|0|c|c|c|i|i|i|i|i|i|i|
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* ---------------------------------
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* | (class) | (module specific) |
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*
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* where c -> Externel Clock Command: Clk & Autoidle Disable/Enable
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* i -> External Clock ID Timers 5,6,7,8, McBSP1,2 and WDT3
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*/
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/* MBX_PM_CLK_IDMASK: DSP External clock id mask. */
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#define MBX_PM_CLK_IDMASK 0x7F
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/* MBX_PM_CLK_CMDSHIFT: DSP External clock command shift. */
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#define MBX_PM_CLK_CMDSHIFT 7
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/* MBX_PM_CLK_CMDMASK: DSP External clock command mask. */
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#define MBX_PM_CLK_CMDMASK 7
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/* MBX_PM_MAX_RESOURCES: CORE 1 Clock resources. */
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#define MBX_CORE1_RESOURCES 7
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/* MBX_PM_MAX_RESOURCES: CORE 2 Clock Resources. */
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#define MBX_CORE2_RESOURCES 1
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/* MBX_PM_MAX_RESOURCES: TOTAL Clock Resources. */
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#define MBX_PM_MAX_RESOURCES 11
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/* Power Management Commands */
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#define BPWR_DISABLE_CLOCK 0
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#define BPWR_ENABLE_CLOCK 1
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/* OMAP242x specific resources */
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enum bpwr_ext_clock_id {
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BPWR_GP_TIMER5 = 0x10,
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BPWR_GP_TIMER6,
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BPWR_GP_TIMER7,
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BPWR_GP_TIMER8,
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BPWR_WD_TIMER3,
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BPWR_MCBSP1,
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BPWR_MCBSP2,
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BPWR_MCBSP3,
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BPWR_MCBSP4,
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BPWR_MCBSP5,
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BPWR_SSI = 0x20
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};
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static const u32 bpwr_clkid[] = {
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(u32) BPWR_GP_TIMER5,
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(u32) BPWR_GP_TIMER6,
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(u32) BPWR_GP_TIMER7,
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(u32) BPWR_GP_TIMER8,
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(u32) BPWR_WD_TIMER3,
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(u32) BPWR_MCBSP1,
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(u32) BPWR_MCBSP2,
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(u32) BPWR_MCBSP3,
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(u32) BPWR_MCBSP4,
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(u32) BPWR_MCBSP5,
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(u32) BPWR_SSI
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};
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struct bpwr_clk_t {
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u32 clk_id;
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enum dsp_clk_id clk;
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};
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static const struct bpwr_clk_t bpwr_clks[] = {
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{(u32) BPWR_GP_TIMER5, DSP_CLK_GPT5},
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{(u32) BPWR_GP_TIMER6, DSP_CLK_GPT6},
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{(u32) BPWR_GP_TIMER7, DSP_CLK_GPT7},
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{(u32) BPWR_GP_TIMER8, DSP_CLK_GPT8},
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{(u32) BPWR_WD_TIMER3, DSP_CLK_WDT3},
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{(u32) BPWR_MCBSP1, DSP_CLK_MCBSP1},
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{(u32) BPWR_MCBSP2, DSP_CLK_MCBSP2},
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{(u32) BPWR_MCBSP3, DSP_CLK_MCBSP3},
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{(u32) BPWR_MCBSP4, DSP_CLK_MCBSP4},
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{(u32) BPWR_MCBSP5, DSP_CLK_MCBSP5},
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{(u32) BPWR_SSI, DSP_CLK_SSI}
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};
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/* Interrupt Register Offsets */
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#define INTH_IT_REG_OFFSET 0x00 /* Interrupt register offset */
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#define INTH_MASK_IT_REG_OFFSET 0x04 /* Mask Interrupt reg offset */
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#define DSP_MAILBOX1_INT 10
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/*
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* Bit definition of Interrupt Level Registers
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*/
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/* Mail Box defines */
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#define MB_ARM2DSP1_REG_OFFSET 0x00
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#define MB_ARM2DSP1B_REG_OFFSET 0x04
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#define MB_DSP2ARM1B_REG_OFFSET 0x0C
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#define MB_ARM2DSP1_FLAG_REG_OFFSET 0x18
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#define MB_ARM2DSP_FLAG 0x0001
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#define MBOX_ARM2DSP HW_MBOX_ID0
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#define MBOX_DSP2ARM HW_MBOX_ID1
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#define MBOX_ARM HW_MBOX_U0_ARM
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#define MBOX_DSP HW_MBOX_U1_DSP1
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#define ENABLE true
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#define DISABLE false
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#define HIGH_LEVEL true
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#define LOW_LEVEL false
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/* Macro's */
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#define CLEAR_BIT(reg, mask) (reg &= ~mask)
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#define SET_BIT(reg, mask) (reg |= mask)
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#define SET_GROUP_BITS16(reg, position, width, value) \
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do {\
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reg &= ~((0xFFFF >> (16 - (width))) << (position)) ; \
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reg |= ((value & (0xFFFF >> (16 - (width)))) << (position)); \
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} while (0);
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#define CLEAR_BIT_INDEX(reg, index) (reg &= ~(1 << (index)))
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/* This Bridge driver's device context: */
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struct bridge_dev_context {
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struct dev_object *dev_obj; /* Handle to Bridge device object. */
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u32 dsp_base_addr; /* Arm's API to DSP virt base addr */
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/*
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* DSP External memory prog address as seen virtually by the OS on
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* the host side.
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*/
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u32 dsp_ext_base_addr; /* See the comment above */
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u32 api_reg_base; /* API mem map'd registers */
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void __iomem *dsp_mmu_base; /* DSP MMU Mapped registers */
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u32 api_clk_base; /* CLK Registers */
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u32 dsp_clk_m2_base; /* DSP Clock Module m2 */
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u32 public_rhea; /* Pub Rhea */
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u32 int_addr; /* MB INTR reg */
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u32 tc_endianism; /* TC Endianism register */
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u32 test_base; /* DSP MMU Mapped registers */
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u32 self_loop; /* Pointer to the selfloop */
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u32 dsp_start_add; /* API Boot vector */
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u32 internal_size; /* Internal memory size */
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struct omap_mbox *mbox; /* Mail box handle */
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struct cfg_hostres *resources; /* Host Resources */
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/*
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* Processor specific info is set when prog loaded and read from DCD.
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* [See bridge_dev_ctrl()] PROC info contains DSP-MMU TLB entries.
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*/
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/* DMMU TLB entries */
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struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB];
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u32 brd_state; /* Last known board state. */
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/* TC Settings */
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bool tc_word_swap_on; /* Traffic Controller Word Swap */
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struct pg_table_attrs *pt_attrs;
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u32 dsp_per_clks;
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};
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/*
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* If dsp_debug is true, do not branch to the DSP entry
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* point and wait for DSP to boot.
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*/
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extern s32 dsp_debug;
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/*
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* ======== sm_interrupt_dsp ========
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* Purpose:
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* Set interrupt value & send an interrupt to the DSP processor(s).
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* This is typically used when mailbox interrupt mechanisms allow data
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* to be associated with interrupt such as for OMAP's CMD/DATA regs.
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* Parameters:
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* dev_context: Handle to Bridge driver defined device info.
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* mb_val: Value associated with interrupt(e.g. mailbox value).
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* Returns:
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* 0: Interrupt sent;
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* else: Unable to send interrupt.
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* Requires:
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* Ensures:
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*/
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int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val);
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#endif /* _TIOMAP_ */
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