100 lines
2.7 KiB
C
100 lines
2.7 KiB
C
/*
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* Symmetric Multi Processing (SMP) support for Marvell EBU Cortex-A9
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* based SOCs (Armada 375/38x).
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/smp.h>
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#include <linux/mbus.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#include "common.h"
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#include "mvebu-soc-id.h"
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#include "pmsu.h"
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#define CRYPT0_ENG_ID 41
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#define CRYPT0_ENG_ATTR 0x1
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#define SRAM_PHYS_BASE 0xFFFF0000
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#define BOOTROM_BASE 0xFFF00000
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#define BOOTROM_SIZE 0x100000
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extern unsigned char armada_375_smp_cpu1_enable_code_end;
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extern unsigned char armada_375_smp_cpu1_enable_code_start;
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static void armada_375_smp_cpu1_enable_wa(void)
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{
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void __iomem *sram_virt_base;
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mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
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mvebu_mbus_add_window_by_id(CRYPT0_ENG_ID, CRYPT0_ENG_ATTR,
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SRAM_PHYS_BASE, SZ_64K);
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sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
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memcpy(sram_virt_base, &armada_375_smp_cpu1_enable_code_start,
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&armada_375_smp_cpu1_enable_code_end
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- &armada_375_smp_cpu1_enable_code_start);
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}
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extern void mvebu_cortex_a9_secondary_startup(void);
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static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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int ret, hw_cpu;
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pr_info("Booting CPU %d\n", cpu);
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/*
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* Write the address of secondary startup into the system-wide
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* flags register. The boot monitor waits until it receives a
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* soft interrupt, and then the secondary CPU branches to this
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* address.
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*/
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hw_cpu = cpu_logical_map(cpu);
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if (of_machine_is_compatible("marvell,armada375")) {
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u32 dev, rev;
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if (mvebu_get_soc_id(&dev, &rev) == 0 &&
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rev == ARMADA_375_Z1_REV)
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armada_375_smp_cpu1_enable_wa();
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mvebu_system_controller_set_cpu_boot_addr(mvebu_cortex_a9_secondary_startup);
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}
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else {
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mvebu_pmsu_set_cpu_boot_addr(hw_cpu,
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mvebu_cortex_a9_secondary_startup);
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}
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smp_wmb();
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ret = mvebu_cpu_reset_deassert(hw_cpu);
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if (ret) {
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pr_err("Could not start the secondary CPU: %d\n", ret);
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return ret;
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}
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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static struct smp_operations mvebu_cortex_a9_smp_ops __initdata = {
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.smp_boot_secondary = mvebu_cortex_a9_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",
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&mvebu_cortex_a9_smp_ops);
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CPU_METHOD_OF_DECLARE(mvebu_armada_380_smp, "marvell,armada-380-smp",
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&mvebu_cortex_a9_smp_ops);
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