David Daney 32546f38fa MIPS: Add TLBR and ROTR to uasm. ... The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and ROTR support in uasm. We also add a UASM_i_ROTR macro. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/953/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2010-02-27 12:53:25 +01:00
..
c-octeon.c	MIPS: Nuke trailing blank lines	2010-02-27 12:53:14 +01:00
c-r3k.c
c-r4k.c
c-tx39.c
cache.c	MIPS: Fix __devinit __cpuinit confusion in cpu_cache_init	2010-02-10 22:15:45 +01:00
cerr-sb1.c	MIPS: Sibyte: Use hweight8 instead of counting bits	2009-12-17 01:57:16 +00:00
cex-gen.S
cex-oct.S
cex-sb1.S
dma-default.c	MIPS: Add DMA declare coherent memory support	2009-11-13 18:10:37 +01:00
extable.c
fault.c	MIPS: Don't corrupt page tables on vmalloc fault.	2009-09-17 20:07:52 +02:00
highmem.c	MIPS: Highmem: Fix build error	2010-02-22 21:42:11 +01:00
hugetlbpage.c	MIPS: Nuke trailing blank lines	2010-02-27 12:53:14 +01:00
init.c	MIPS: Two-level pagetables for 64-bit kernels with 64KB pages.	2010-02-27 12:53:03 +01:00
ioremap.c
Makefile
page.c	MIPS: Move arch/mips/mm/uasm.h to arch/mips/include/asm/uasm.h	2010-02-27 12:53:19 +01:00
pgtable-32.c
pgtable-64.c	MIPS: Two-level pagetables for 64-bit kernels with 64KB pages.	2010-02-27 12:53:03 +01:00
sc-ip22.c
sc-mips.c	MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.	2009-09-30 21:47:00 +02:00
sc-r5k.c
sc-rm7k.c
tlb-r3k.c
tlb-r4k.c	MIPS: Remove #if 0 r4k_update_mmu_cache_hwbug	2010-02-27 12:53:23 +01:00
tlb-r8k.c
tlbex-fault.S
tlbex.c	MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.	2010-02-27 12:53:25 +01:00
uasm.c	MIPS: Add TLBR and ROTR to uasm.	2010-02-27 12:53:25 +01:00