1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
935 lines
24 KiB
ArmAsm
935 lines
24 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-xscale.S
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*
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* Author: Nicolas Pitre
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* Created: November 2000
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* Copyright: (C) 2000, 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* MMU functions for the Intel XScale CPUs
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*
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* 2001 Aug 21:
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* some contributions by Brett Gaines <brett.w.gaines@intel.com>
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* Copyright 2001 by Intel Corp.
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*
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* 2001 Sep 08:
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* Completely revisited, many important fixes
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* Nicolas Pitre <nico@cam.org>
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/procinfo.h>
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#include <asm/hardware.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be flushed. If the area
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* is larger than this, then we flush the whole cache
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*/
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#define MAX_AREA_SIZE 32768
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/*
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* the cache line size of the I and D cache
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*/
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#define CACHELINESIZE 32
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/*
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* the size of the data cache
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*/
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#define CACHESIZE 32768
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/*
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* Virtual address used to allocate the cache when flushed
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*
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* This must be an address range which is _never_ used. It should
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* apparently have a mapping in the corresponding page table for
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* compatibility with future CPUs that _could_ require it. For instance we
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* don't care.
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*
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* This must be aligned on a 2*CACHESIZE boundary. The code selects one of
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* the 2 areas in alternance each time the clean_d_cache macro is used.
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* Without this the XScale core exhibits cache eviction problems and no one
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* knows why.
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*
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* Reminder: the vector table is located at 0xffff0000-0xffff0fff.
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*/
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#define CLEAN_ADDR 0xfffe0000
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/*
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* This macro is used to wait for a CP15 write and is needed
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* when we have to ensure that the last operation to the co-pro
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* was completed before continuing with operation.
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*/
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.macro cpwait, rd
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mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
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mov \rd, \rd @ wait for completion
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sub pc, pc, #4 @ flush instruction pipeline
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.endm
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.macro cpwait_ret, lr, rd
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mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
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sub pc, \lr, \rd, LSR #32 @ wait for completion and
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@ flush instruction pipeline
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.endm
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/*
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* This macro cleans the entire dcache using line allocate.
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* The main loop has been unrolled to reduce loop overhead.
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* rd and rs are two scratch registers.
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*/
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.macro clean_d_cache, rd, rs
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ldr \rs, =clean_addr
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ldr \rd, [\rs]
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eor \rd, \rd, #CACHESIZE
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str \rd, [\rs]
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add \rs, \rd, #CACHESIZE
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1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
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add \rd, \rd, #CACHELINESIZE
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mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
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add \rd, \rd, #CACHELINESIZE
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mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
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add \rd, \rd, #CACHELINESIZE
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mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
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add \rd, \rd, #CACHELINESIZE
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teq \rd, \rs
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bne 1b
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.endm
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.data
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clean_addr: .word CLEAN_ADDR
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.text
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/*
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* cpu_xscale_proc_init()
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*
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* Nothing too exciting at the moment
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*/
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ENTRY(cpu_xscale_proc_init)
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mov pc, lr
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/*
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* cpu_xscale_proc_fin()
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*/
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ENTRY(cpu_xscale_proc_fin)
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str lr, [sp, #-4]!
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mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r0
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bl xscale_flush_kern_cache_all @ clean caches
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1800 @ ...IZ...........
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bic r0, r0, #0x0006 @ .............CA.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldr pc, [sp], #4
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/*
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* cpu_xscale_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_xscale_reset)
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mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r1 @ reset CPSR
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mrc p15, 0, r1, c1, c0, 0 @ ctrl register
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bic r1, r1, #0x0086 @ ........B....CA.
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bic r1, r1, #0x3900 @ ..VIZ..S........
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mcr p15, 0, r1, c1, c0, 0 @ ctrl register
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
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bic r1, r1, #0x0001 @ ...............M
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mcr p15, 0, r1, c1, c0, 0 @ ctrl register
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@ CAUTION: MMU turned off from this point. We count on the pipeline
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@ already containing those two last instructions to survive.
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mov pc, r0
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/*
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* cpu_xscale_do_idle()
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*
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* Cause the processor to idle
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*
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* For now we do nothing but go to idle mode for every case
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*
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* XScale supports clock switching, but using idle mode support
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* allows external hardware to react to system state changes.
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*/
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.align 5
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ENTRY(cpu_xscale_do_idle)
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mov r0, #1
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mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
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mov pc, lr
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/* ================================= CACHE ================================ */
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/*
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* flush_user_cache_all()
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*
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* Invalidate all cache entries in a particular address
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* space.
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*/
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ENTRY(xscale_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(xscale_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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clean_d_cache r0, r1
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
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mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, vm_flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - vma - vma_area_struct describing address space
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*/
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.align 5
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ENTRY(xscale_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #MAX_AREA_SIZE
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bhs __flush_whole_cache
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1: tst r2, #VM_EXEC
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mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
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mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
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mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
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mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* Note: single I-cache line invalidation isn't used here since
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* it also trashes the mini I-cache used by JTAG debuggers.
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*/
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ENTRY(xscale_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* Note: single I-cache line invalidation isn't used here since
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* it also trashes the mini I-cache used by JTAG debuggers.
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*/
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ENTRY(xscale_coherent_user_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov pc, lr
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - page aligned address
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*/
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ENTRY(xscale_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(xscale_dma_inv_range)
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mrc p15, 0, r2, c0, c0, 0 @ read ID
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eor r2, r2, #0x69000000
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eor r2, r2, #0x00052000
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bics r2, r2, #1
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beq xscale_dma_flush_range
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tst r0, #CACHELINESIZE - 1
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bic r0, r0, #CACHELINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHELINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(xscale_dma_clean_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(xscale_dma_flush_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov pc, lr
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ENTRY(xscale_cache_fns)
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.long xscale_flush_kern_cache_all
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.long xscale_flush_user_cache_all
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.long xscale_flush_user_cache_range
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.long xscale_coherent_kern_range
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.long xscale_coherent_user_range
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.long xscale_flush_kern_dcache_page
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.long xscale_dma_inv_range
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.long xscale_dma_clean_range
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.long xscale_dma_flush_range
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ENTRY(cpu_xscale_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHELINESIZE
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subs r1, r1, #CACHELINESIZE
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bhi 1b
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mov pc, lr
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/* ================================ CACHE LOCKING============================
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*
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* The XScale MicroArchitecture implements support for locking entries into
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* the data and instruction cache. The following functions implement the core
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* low level instructions needed to accomplish the locking. The developer's
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* manual states that the code that performs the locking must be in non-cached
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* memory. To accomplish this, the code in xscale-cache-lock.c copies the
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* following functions from the cache into a non-cached memory region that
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* is allocated through consistent_alloc().
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*
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*/
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.align 5
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/*
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* xscale_icache_lock
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*
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* r0: starting address to lock
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* r1: end address to lock
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*/
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ENTRY(xscale_icache_lock)
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iLockLoop:
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bic r0, r0, #CACHELINESIZE - 1
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mcr p15, 0, r0, c9, c1, 0 @ lock into cache
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cmp r0, r1 @ are we done?
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add r0, r0, #CACHELINESIZE @ advance to next cache line
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bls iLockLoop
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mov pc, lr
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/*
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* xscale_icache_unlock
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*/
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ENTRY(xscale_icache_unlock)
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mcr p15, 0, r0, c9, c1, 1 @ Unlock icache
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mov pc, lr
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/*
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* xscale_dcache_lock
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*
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* r0: starting address to lock
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* r1: end address to lock
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*/
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ENTRY(xscale_dcache_lock)
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov r2, #1
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mcr p15, 0, r2, c9, c2, 0 @ Put dcache in lock mode
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cpwait ip @ Wait for completion
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mrs r2, cpsr
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orr r3, r2, #PSR_F_BIT | PSR_I_BIT
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dLockLoop:
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msr cpsr_c, r3
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mcr p15, 0, r0, c7, c10, 1 @ Write back line if it is dirty
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mcr p15, 0, r0, c7, c6, 1 @ Flush/invalidate line
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msr cpsr_c, r2
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ldr ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from
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@ location [r0]. Post-increment
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@ r3 to next cache line
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cmp r0, r1 @ Are we done?
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bls dLockLoop
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov r2, #0
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mcr p15, 0, r2, c9, c2, 0 @ Get out of lock mode
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cpwait_ret lr, ip
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/*
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* xscale_dcache_unlock
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*/
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ENTRY(xscale_dcache_unlock)
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mcr p15, 0, ip, c9, c2, 1 @ Unlock cache
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mov pc, lr
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/*
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* Needed to determine the length of the code that needs to be copied.
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*/
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.align 5
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ENTRY(xscale_cache_dummy)
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mov pc, lr
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/* ================================ TLB LOCKING==============================
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*
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* The XScale MicroArchitecture implements support for locking entries into
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* the Instruction and Data TLBs. The following functions provide the
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* low level support for supporting these under Linux. xscale-lock.c
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* implements some higher level management code. Most of the following
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* is taken straight out of the Developer's Manual.
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*/
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/*
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* Lock I-TLB entry
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*
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* r0: Virtual address to translate and lock
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*/
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.align 5
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ENTRY(xscale_itlb_lock)
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mrs r2, cpsr
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orr r3, r2, #PSR_F_BIT | PSR_I_BIT
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msr cpsr_c, r3 @ Disable interrupts
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mcr p15, 0, r0, c8, c5, 1 @ Invalidate I-TLB entry
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mcr p15, 0, r0, c10, c4, 0 @ Translate and lock
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msr cpsr_c, r2 @ Restore interrupts
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cpwait_ret lr, ip
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/*
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* Lock D-TLB entry
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*
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* r0: Virtual address to translate and lock
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*/
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.align 5
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ENTRY(xscale_dtlb_lock)
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mrs r2, cpsr
|
|
orr r3, r2, #PSR_F_BIT | PSR_I_BIT
|
|
msr cpsr_c, r3 @ Disable interrupts
|
|
mcr p15, 0, r0, c8, c6, 1 @ Invalidate D-TLB entry
|
|
mcr p15, 0, r0, c10, c8, 0 @ Translate and lock
|
|
msr cpsr_c, r2 @ Restore interrupts
|
|
cpwait_ret lr, ip
|
|
|
|
/*
|
|
* Unlock all I-TLB entries
|
|
*/
|
|
.align 5
|
|
ENTRY(xscale_itlb_unlock)
|
|
mcr p15, 0, ip, c10, c4, 1 @ Unlock I-TLB
|
|
mcr p15, 0, ip, c8, c5, 0 @ Invalidate I-TLB
|
|
cpwait_ret lr, ip
|
|
|
|
/*
|
|
* Unlock all D-TLB entries
|
|
*/
|
|
ENTRY(xscale_dtlb_unlock)
|
|
mcr p15, 0, ip, c10, c8, 1 @ Unlock D-TBL
|
|
mcr p15, 0, ip, c8, c6, 0 @ Invalidate D-TLB
|
|
cpwait_ret lr, ip
|
|
|
|
/* =============================== PageTable ============================== */
|
|
|
|
#define PTE_CACHE_WRITE_ALLOCATE 0
|
|
|
|
/*
|
|
* cpu_xscale_switch_mm(pgd)
|
|
*
|
|
* Set the translation base pointer to be as described by pgd.
|
|
*
|
|
* pgd: new page tables
|
|
*/
|
|
.align 5
|
|
ENTRY(cpu_xscale_switch_mm)
|
|
clean_d_cache r1, r2
|
|
mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
|
|
mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
|
|
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
|
cpwait_ret lr, ip
|
|
|
|
/*
|
|
* cpu_xscale_set_pte(ptep, pte)
|
|
*
|
|
* Set a PTE and flush it out
|
|
*
|
|
* Errata 40: must set memory to write-through for user read-only pages.
|
|
*/
|
|
.align 5
|
|
ENTRY(cpu_xscale_set_pte)
|
|
str r1, [r0], #-2048 @ linux version
|
|
|
|
bic r2, r1, #0xff0
|
|
orr r2, r2, #PTE_TYPE_EXT @ extended page
|
|
|
|
eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
|
|
|
|
tst r3, #L_PTE_USER @ User?
|
|
orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
|
|
|
|
tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
|
|
orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
|
|
@ combined with user -> user r/w
|
|
|
|
@
|
|
@ Handle the X bit. We want to set this bit for the minicache
|
|
@ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
|
|
@ and we have a writeable, cacheable region. If we ignore the
|
|
@ U and E bits, we can allow user space to use the minicache as
|
|
@ well.
|
|
@
|
|
@ X = (C & ~W & ~B) | (C & W & B & write_allocate)
|
|
@
|
|
eor ip, r1, #L_PTE_CACHEABLE
|
|
tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
|
|
#if PTE_CACHE_WRITE_ALLOCATE
|
|
eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
|
|
tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
|
|
#endif
|
|
orreq r2, r2, #PTE_EXT_TEX(1)
|
|
|
|
@
|
|
@ Erratum 40: The B bit must be cleared for a user read-only
|
|
@ cacheable page.
|
|
@
|
|
@ B = B & ~(U & C & ~W)
|
|
@
|
|
and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
|
|
teq ip, #L_PTE_USER | L_PTE_CACHEABLE
|
|
biceq r2, r2, #PTE_BUFFERABLE
|
|
|
|
tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
|
|
movne r2, #0 @ no -> fault
|
|
|
|
str r2, [r0] @ hardware version
|
|
mov ip, #0
|
|
mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
|
|
mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
|
|
mov pc, lr
|
|
|
|
|
|
.ltorg
|
|
|
|
.align
|
|
|
|
__INIT
|
|
|
|
.type __xscale_setup, #function
|
|
__xscale_setup:
|
|
mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
|
|
mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
|
|
#ifdef CONFIG_IWMMXT
|
|
mov r0, #0 @ initially disallow access to CP0/CP1
|
|
#else
|
|
mov r0, #1 @ Allow access to CP0
|
|
#endif
|
|
orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
|
|
orr r0, r0, #1 << 13 @ Its undefined whether this
|
|
mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
|
|
mrc p15, 0, r0, c1, c0, 0 @ get control register
|
|
ldr r5, xscale_cr1_clear
|
|
bic r0, r0, r5
|
|
ldr r5, xscale_cr1_set
|
|
orr r0, r0, r5
|
|
mov pc, lr
|
|
.size __xscale_setup, . - __xscale_setup
|
|
|
|
/*
|
|
* R
|
|
* .RVI ZFRS BLDP WCAM
|
|
* ..11 1.01 .... .101
|
|
*
|
|
*/
|
|
.type xscale_cr1_clear, #object
|
|
.type xscale_cr1_set, #object
|
|
xscale_cr1_clear:
|
|
.word 0x3b07
|
|
xscale_cr1_set:
|
|
.word 0x3905
|
|
|
|
__INITDATA
|
|
|
|
/*
|
|
* Purpose : Function pointers used to access above functions - all calls
|
|
* come through these
|
|
*/
|
|
|
|
.type xscale_processor_functions, #object
|
|
ENTRY(xscale_processor_functions)
|
|
.word v5t_early_abort
|
|
.word cpu_xscale_proc_init
|
|
.word cpu_xscale_proc_fin
|
|
.word cpu_xscale_reset
|
|
.word cpu_xscale_do_idle
|
|
.word cpu_xscale_dcache_clean_area
|
|
.word cpu_xscale_switch_mm
|
|
.word cpu_xscale_set_pte
|
|
.size xscale_processor_functions, . - xscale_processor_functions
|
|
|
|
.section ".rodata"
|
|
|
|
.type cpu_arch_name, #object
|
|
cpu_arch_name:
|
|
.asciz "armv5te"
|
|
.size cpu_arch_name, . - cpu_arch_name
|
|
|
|
.type cpu_elf_name, #object
|
|
cpu_elf_name:
|
|
.asciz "v5"
|
|
.size cpu_elf_name, . - cpu_elf_name
|
|
|
|
.type cpu_80200_name, #object
|
|
cpu_80200_name:
|
|
.asciz "XScale-80200"
|
|
.size cpu_80200_name, . - cpu_80200_name
|
|
|
|
.type cpu_8032x_name, #object
|
|
cpu_8032x_name:
|
|
.asciz "XScale-IOP8032x Family"
|
|
.size cpu_8032x_name, . - cpu_8032x_name
|
|
|
|
.type cpu_8033x_name, #object
|
|
cpu_8033x_name:
|
|
.asciz "XScale-IOP8033x Family"
|
|
.size cpu_8033x_name, . - cpu_8033x_name
|
|
|
|
.type cpu_pxa250_name, #object
|
|
cpu_pxa250_name:
|
|
.asciz "XScale-PXA250"
|
|
.size cpu_pxa250_name, . - cpu_pxa250_name
|
|
|
|
.type cpu_pxa210_name, #object
|
|
cpu_pxa210_name:
|
|
.asciz "XScale-PXA210"
|
|
.size cpu_pxa210_name, . - cpu_pxa210_name
|
|
|
|
.type cpu_ixp42x_name, #object
|
|
cpu_ixp42x_name:
|
|
.asciz "XScale-IXP42x Family"
|
|
.size cpu_ixp42x_name, . - cpu_ixp42x_name
|
|
|
|
.type cpu_ixp46x_name, #object
|
|
cpu_ixp46x_name:
|
|
.asciz "XScale-IXP46x Family"
|
|
.size cpu_ixp46x_name, . - cpu_ixp46x_name
|
|
|
|
.type cpu_ixp2400_name, #object
|
|
cpu_ixp2400_name:
|
|
.asciz "XScale-IXP2400"
|
|
.size cpu_ixp2400_name, . - cpu_ixp2400_name
|
|
|
|
.type cpu_ixp2800_name, #object
|
|
cpu_ixp2800_name:
|
|
.asciz "XScale-IXP2800"
|
|
.size cpu_ixp2800_name, . - cpu_ixp2800_name
|
|
|
|
.type cpu_pxa255_name, #object
|
|
cpu_pxa255_name:
|
|
.asciz "XScale-PXA255"
|
|
.size cpu_pxa255_name, . - cpu_pxa255_name
|
|
|
|
.type cpu_pxa270_name, #object
|
|
cpu_pxa270_name:
|
|
.asciz "XScale-PXA270"
|
|
.size cpu_pxa270_name, . - cpu_pxa270_name
|
|
|
|
.align
|
|
|
|
.section ".proc.info", #alloc, #execinstr
|
|
|
|
.type __80200_proc_info,#object
|
|
__80200_proc_info:
|
|
.long 0x69052000
|
|
.long 0xfffffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_80200_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __80200_proc_info, . - __80200_proc_info
|
|
|
|
.type __8032x_proc_info,#object
|
|
__8032x_proc_info:
|
|
.long 0x69052420
|
|
.long 0xfffff5e0 @ mask should accomodate IOP80219 also
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_8032x_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __8032x_proc_info, . - __8032x_proc_info
|
|
|
|
.type __8033x_proc_info,#object
|
|
__8033x_proc_info:
|
|
.long 0x69054010
|
|
.long 0xffffff30
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_8033x_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __8033x_proc_info, . - __8033x_proc_info
|
|
|
|
.type __pxa250_proc_info,#object
|
|
__pxa250_proc_info:
|
|
.long 0x69052100
|
|
.long 0xfffff7f0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_pxa250_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __pxa250_proc_info, . - __pxa250_proc_info
|
|
|
|
.type __pxa210_proc_info,#object
|
|
__pxa210_proc_info:
|
|
.long 0x69052120
|
|
.long 0xfffff3f0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_pxa210_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __pxa210_proc_info, . - __pxa210_proc_info
|
|
|
|
.type __ixp2400_proc_info, #object
|
|
__ixp2400_proc_info:
|
|
.long 0x69054190
|
|
.long 0xfffffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_ixp2400_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __ixp2400_proc_info, . - __ixp2400_proc_info
|
|
|
|
.type __ixp2800_proc_info, #object
|
|
__ixp2800_proc_info:
|
|
.long 0x690541a0
|
|
.long 0xfffffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_ixp2800_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __ixp2800_proc_info, . - __ixp2800_proc_info
|
|
|
|
.type __ixp42x_proc_info, #object
|
|
__ixp42x_proc_info:
|
|
.long 0x690541c0
|
|
.long 0xffffffc0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_ixp42x_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __ixp42x_proc_info, . - __ixp42x_proc_info
|
|
|
|
.type __ixp46x_proc_info, #object
|
|
__ixp46x_proc_info:
|
|
.long 0x69054200
|
|
.long 0xffffff00
|
|
.long 0x00000c0e
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_ixp46x_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __ixp46x_proc_info, . - __ixp46x_proc_info
|
|
|
|
.type __pxa255_proc_info,#object
|
|
__pxa255_proc_info:
|
|
.long 0x69052d00
|
|
.long 0xfffffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_pxa255_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __pxa255_proc_info, . - __pxa255_proc_info
|
|
|
|
.type __pxa270_proc_info,#object
|
|
__pxa270_proc_info:
|
|
.long 0x69054110
|
|
.long 0xfffffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __xscale_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_pxa270_name
|
|
.long xscale_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xscale_mc_user_fns
|
|
.long xscale_cache_fns
|
|
.size __pxa270_proc_info, . - __pxa270_proc_info
|
|
|