a0e1b61858
Like Zynq the Altera drivers compile fine on x86 and others too, so make it easier to compile test this stuff. A10 requires REGMAP_MMIO to compile, so be explicit rather than relying on it via ARCH_SOCFPGA. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Alan Tull <atull@opensource.altera.com>
69 lines
1.7 KiB
Plaintext
69 lines
1.7 KiB
Plaintext
#
|
|
# FPGA framework configuration
|
|
#
|
|
|
|
menu "FPGA Configuration Support"
|
|
|
|
config FPGA
|
|
tristate "FPGA Configuration Framework"
|
|
help
|
|
Say Y here if you want support for configuring FPGAs from the
|
|
kernel. The FPGA framework adds a FPGA manager class and FPGA
|
|
manager drivers.
|
|
|
|
if FPGA
|
|
|
|
config FPGA_REGION
|
|
tristate "FPGA Region"
|
|
depends on OF && FPGA_BRIDGE
|
|
help
|
|
FPGA Regions allow loading FPGA images under control of
|
|
the Device Tree.
|
|
|
|
config FPGA_MGR_SOCFPGA
|
|
tristate "Altera SOCFPGA FPGA Manager"
|
|
depends on ARCH_SOCFPGA || COMPILE_TEST
|
|
help
|
|
FPGA manager driver support for Altera SOCFPGA.
|
|
|
|
config FPGA_MGR_SOCFPGA_A10
|
|
tristate "Altera SoCFPGA Arria10"
|
|
depends on ARCH_SOCFPGA || COMPILE_TEST
|
|
select REGMAP_MMIO
|
|
help
|
|
FPGA manager driver support for Altera Arria10 SoCFPGA.
|
|
|
|
config FPGA_MGR_ZYNQ_FPGA
|
|
tristate "Xilinx Zynq FPGA"
|
|
depends on ARCH_ZYNQ || COMPILE_TEST
|
|
depends on HAS_DMA
|
|
help
|
|
FPGA manager driver support for Xilinx Zynq FPGAs.
|
|
|
|
config FPGA_BRIDGE
|
|
tristate "FPGA Bridge Framework"
|
|
depends on OF
|
|
help
|
|
Say Y here if you want to support bridges connected between host
|
|
processors and FPGAs or between FPGAs.
|
|
|
|
config SOCFPGA_FPGA_BRIDGE
|
|
tristate "Altera SoCFPGA FPGA Bridges"
|
|
depends on ARCH_SOCFPGA && FPGA_BRIDGE
|
|
help
|
|
Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
|
|
devices.
|
|
|
|
config ALTERA_FREEZE_BRIDGE
|
|
tristate "Altera FPGA Freeze Bridge"
|
|
depends on ARCH_SOCFPGA && FPGA_BRIDGE
|
|
help
|
|
Say Y to enable drivers for Altera FPGA Freeze bridges. A
|
|
freeze bridge is a bridge that exists in the FPGA fabric to
|
|
isolate one region of the FPGA from the busses while that
|
|
region is being reprogrammed.
|
|
|
|
endif # FPGA
|
|
|
|
endmenu
|