Jesse Brandeburg 3ae84d9269 ixgb: fix cache miss due to miscalculation
Reduce writeback threshold by 1. We were instructing the hardware to
wait until the 17th descriptor which went over the cache line limit.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Auke Kok <auke.jan.h.kok@intel.com>
2006-08-16 13:47:25 -07:00
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