linux/drivers/clk/socfpga
Dinh Nguyen 34d5003bfb clk: socfpga: Add a second parent option for the dbg_base_clk
The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.

This patch adds the option to get the correct parent for the debug base
clock.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:03 -07:00
..
Makefile clk: socfpga: add a clock driver for the Arria 10 platform 2015-05-21 15:16:04 -07:00
clk-gate-a10.c clk: socfpga: switch to GENMASK() 2015-07-28 11:59:16 -07:00
clk-gate.c clk: socfpga: switch to GENMASK() 2015-07-28 11:59:16 -07:00
clk-periph-a10.c clk: socfpga: switch to GENMASK() 2015-07-28 11:59:16 -07:00
clk-periph.c clk: socfpga: Add a second parent option for the dbg_base_clk 2015-08-24 16:49:03 -07:00
clk-pll-a10.c clk: socfpga: Remove clk.h and clkdev.h includes 2015-07-20 11:11:14 -07:00
clk-pll.c clk: socfpga: Remove clk.h and clkdev.h includes 2015-07-20 11:11:14 -07:00
clk.c clk: socfpga: add a clock driver for the Arria 10 platform 2015-05-21 15:16:04 -07:00
clk.h clk: socfpga: Add a second parent option for the dbg_base_clk 2015-08-24 16:49:03 -07:00