Ralf Baechle 3d45285dd1 MIPS: Sibyte: Fix M3 TLB exception handler workaround. ... The M3 workaround needs to cmpare the region and VPN2 fields only. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2010-04-12 17:26:21 +01:00
..
c-octeon.c	MIPS: Give Octeon+ CPUs their own cputype.	2010-02-27 12:53:26 +01:00
c-r3k.c
c-r4k.c
c-tx39.c
cache.c	MIPS: Implement Read Inhibit/eXecute Inhibit	2010-02-27 12:53:26 +01:00
cerr-sb1.c	MIPS: Sibyte: Use hweight8 instead of counting bits	2009-12-17 01:57:16 +00:00
cex-gen.S
cex-oct.S
cex-sb1.S
dma-default.c	include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h	2010-03-30 22:02:32 +09:00
extable.c
fault.c	MIPS: Implement Read Inhibit/eXecute Inhibit	2010-02-27 12:53:26 +01:00
highmem.c	MIPS: Highmem: Fix build error	2010-02-22 21:42:11 +01:00
hugetlbpage.c	include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h	2010-03-30 22:02:32 +09:00
init.c	include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h	2010-03-30 22:02:32 +09:00
ioremap.c	include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h	2010-03-30 22:02:32 +09:00
Makefile
page.c	MIPS: Move arch/mips/mm/uasm.h to arch/mips/include/asm/uasm.h	2010-02-27 12:53:19 +01:00
pgtable-32.c
pgtable-64.c	MIPS: Two-level pagetables for 64-bit kernels with 64KB pages.	2010-02-27 12:53:03 +01:00
sc-ip22.c
sc-mips.c	MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.	2009-09-30 21:47:00 +02:00
sc-r5k.c
sc-rm7k.c
tlb-r3k.c
tlb-r4k.c	MIPS: Implement Read Inhibit/eXecute Inhibit	2010-02-27 12:53:26 +01:00
tlb-r8k.c
tlbex-fault.S
tlbex.c	MIPS: Sibyte: Fix M3 TLB exception handler workaround.	2010-04-12 17:26:21 +01:00
uasm.c	MIPS: uasm: Add OR instruction.	2010-04-12 17:26:20 +01:00