2602a21231
The P1023 processor is an e500v2 based SoC that utilizes the DPAA networking architecture. This adds basic board support for non-DPAA functionality (device tree, board file, etc). Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
547 lines
13 KiB
Plaintext
547 lines
13 KiB
Plaintext
/*
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* P1023 RDS Device Tree Source
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*
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* Copyright 2010-2011 Freescale Semiconductor Inc.
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*
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* Author: Roy Zang <tie-fei.zang@freescale.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/ {
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model = "fsl,P1023";
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compatible = "fsl,P1023RDS";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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crypto = &crypto;
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sec_jr0 = &sec_jr0;
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sec_jr1 = &sec_jr1;
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sec_jr2 = &sec_jr2;
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sec_jr3 = &sec_jr3;
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rtic_a = &rtic_a;
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rtic_b = &rtic_b;
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rtic_c = &rtic_c;
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rtic_d = &rtic_d;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,P1023@0 {
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device_type = "cpu";
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reg = <0x0>;
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next-level-cache = <&L2>;
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};
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cpu1: PowerPC,P1023@1 {
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device_type = "cpu";
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reg = <0x1>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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};
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soc@ff600000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,p1023-immr", "simple-bus";
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ranges = <0x0 0x0 0xff600000 0x200000>;
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bus-frequency = <0>; // Filled out by uboot.
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,p1023-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <16 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,p1023-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds1374";
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reg = <0x68>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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spi@7000 {
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cell-index = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,p1023-espi", "fsl,mpc8536-espi";
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reg = <0x7000 0x1000>;
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interrupts = <59 0x2>;
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interrupt-parent = <&mpic>;
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fsl,espi-num-chipselects = <4>;
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fsl_dataflash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at45db081d";
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reg = <0>;
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spi-max-frequency = <40000000>; /* input clock */
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partition@u-boot {
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/* 512KB for u-boot Bootloader Image */
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label = "u-boot-spi";
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reg = <0x00000000 0x00080000>;
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read-only;
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};
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partition@dtb {
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/* 512KB for DTB Image */
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label = "dtb-spi";
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reg = <0x00080000 0x00080000>;
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read-only;
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};
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};
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};
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gpio: gpio-controller@f000 {
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#gpio-cells = <2>;
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compatible = "fsl,qoriq-gpio";
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reg = <0xf000 0x100>;
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interrupts = <47 0x2>;
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interrupt-parent = <&mpic>;
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gpio-controller;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,p1023-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x40000>; // L2,256K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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usb@22000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-usb2-dr";
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reg = <0x22000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <28 0x2>;
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dr_mode = "host";
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phy_type = "ulpi";
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};
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crypto: crypto@300000 {
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compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x30000 0x10000>;
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ranges = <0 0x30000 0x10000>;
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interrupt-parent = <&mpic>;
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interrupts = <58 2>;
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sec_jr0: jr@1000 {
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compatible = "fsl,sec-v4.2-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x1000 0x1000>;
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interrupts = <45 2>;
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};
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sec_jr1: jr@2000 {
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compatible = "fsl,sec-v4.2-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x2000 0x1000>;
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interrupts = <45 2>;
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};
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sec_jr2: jr@3000 {
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compatible = "fsl,sec-v4.2-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x3000 0x1000>;
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interrupts = <57 2>;
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};
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sec_jr3: jr@4000 {
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compatible = "fsl,sec-v4.2-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x4000 0x1000>;
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interrupts = <57 2>;
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};
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rtic@6000 {
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compatible = "fsl,sec-v4.2-rtic",
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"fsl,sec-v4.0-rtic";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x6000 0x100>;
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ranges = <0x0 0x6100 0xe00>;
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rtic_a: rtic-a@0 {
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compatible = "fsl,sec-v4.2-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x00 0x20 0x100 0x80>;
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};
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rtic_b: rtic-b@20 {
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compatible = "fsl,sec-v4.2-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x20 0x20 0x200 0x80>;
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};
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rtic_c: rtic-c@40 {
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compatible = "fsl,sec-v4.2-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x40 0x20 0x300 0x80>;
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};
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rtic_d: rtic-d@60 {
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compatible = "fsl,sec-v4.2-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x60 0x20 0x500 0x80>;
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};
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};
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};
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power@e0070{
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compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
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"fsl,p1022-pmc";
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reg = <0xe0070 0x20>;
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etsec1_clk: soc-clk@B0{
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fsl,pmcdr-mask = <0x00000080>;
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};
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etsec2_clk: soc-clk@B1{
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fsl,pmcdr-mask = <0x00000040>;
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};
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etsec3_clk: soc-clk@B2{
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fsl,pmcdr-mask = <0x00000020>;
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};
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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msi@41600 {
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compatible = "fsl,p1023-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities block
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compatible = "fsl,p1023-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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};
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localbus@ff605000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
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reg = <0 0xff605000 0 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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/* NOR Flash, BCSR */
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ranges = <0x0 0x0 0x0 0xee000000 0x02000000
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0x1 0x0 0x0 0xe0000000 0x00008000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x02000000>;
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bank-width = <1>;
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device-width = <1>;
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partition@0 {
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label = "ramdisk";
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reg = <0x00000000 0x01c00000>;
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};
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partition@1c00000 {
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label = "kernel";
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reg = <0x01c00000 0x002e0000>;
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};
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partiton@1ee0000 {
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label = "dtb";
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reg = <0x01ee0000 0x00020000>;
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};
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partition@1f00000 {
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label = "firmware";
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reg = <0x01f00000 0x00080000>;
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read-only;
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};
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partition@1f80000 {
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label = "u-boot";
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reg = <0x01f80000 0x00080000>;
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read-only;
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};
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};
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fpga@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p1023rds-fpga";
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reg = <1 0 0x8000>;
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ranges = <0 1 0 0x8000>;
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bcsr@20 {
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compatible = "fsl,p1023rds-bcsr";
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reg = <0x20 0x20>;
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};
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};
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};
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pci0: pcie@ff60a000 {
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compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
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cell-index = <1>;
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0 0xff60a000 0 0x1000>;
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bus-range = <0 255>;
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 0 1
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0000 0 0 2 &mpic 1 1
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0000 0 0 3 &mpic 2 1
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0000 0 0 4 &mpic 3 1
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>;
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ff609000 {
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compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
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cell-index = <2>;
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0 0xff609000 0 0x1000>;
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bus-range = <0 255>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 4 1
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0000 0 0 2 &mpic 5 1
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0000 0 0 3 &mpic 6 1
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0000 0 0 4 &mpic 7 1
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>;
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci2: pcie@ff60b000 {
|
|
cell-index = <3>;
|
|
compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
|
|
device_type = "pci";
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0 0xff60b000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
|
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
|
clock-frequency = <33333333>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <16 2>;
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <16 2>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0 0 1 &mpic 8 1
|
|
0000 0 0 2 &mpic 9 1
|
|
0000 0 0 3 &mpic 10 1
|
|
0000 0 0 4 &mpic 11 1
|
|
>;
|
|
ranges = <0x2000000 0x0 0x80000000
|
|
0x2000000 0x0 0x80000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x100000>;
|
|
};
|
|
};
|
|
};
|