403 lines
12 KiB
C
403 lines
12 KiB
C
#ifndef __SOUND_YMFPCI_H
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#define __SOUND_YMFPCI_H
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/*
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* Copyright (c) by Jaroslav Kysela <perex@suse.cz>
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* Definitions for Yahama YMF724/740/744/754 chips
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include "pcm.h"
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#include "rawmidi.h"
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#include "ac97_codec.h"
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#include "timer.h"
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#include <linux/gameport.h>
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#ifndef PCI_VENDOR_ID_YAMAHA
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#define PCI_VENDOR_ID_YAMAHA 0x1073
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#endif
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#ifndef PCI_DEVICE_ID_YAMAHA_724
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#define PCI_DEVICE_ID_YAMAHA_724 0x0004
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#endif
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#ifndef PCI_DEVICE_ID_YAMAHA_724F
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#define PCI_DEVICE_ID_YAMAHA_724F 0x000d
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#endif
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#ifndef PCI_DEVICE_ID_YAMAHA_740
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#define PCI_DEVICE_ID_YAMAHA_740 0x000a
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#endif
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#ifndef PCI_DEVICE_ID_YAMAHA_740C
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#define PCI_DEVICE_ID_YAMAHA_740C 0x000c
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#endif
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#ifndef PCI_DEVICE_ID_YAMAHA_744
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#define PCI_DEVICE_ID_YAMAHA_744 0x0010
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#endif
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#ifndef PCI_DEVICE_ID_YAMAHA_754
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#define PCI_DEVICE_ID_YAMAHA_754 0x0012
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#endif
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/*
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* Direct registers
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*/
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#define YMFREG(chip, reg) (chip->port + YDSXGR_##reg)
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#define YDSXGR_INTFLAG 0x0004
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#define YDSXGR_ACTIVITY 0x0006
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#define YDSXGR_GLOBALCTRL 0x0008
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#define YDSXGR_ZVCTRL 0x000A
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#define YDSXGR_TIMERCTRL 0x0010
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#define YDSXGR_TIMERCOUNT 0x0012
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#define YDSXGR_SPDIFOUTCTRL 0x0018
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#define YDSXGR_SPDIFOUTSTATUS 0x001C
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#define YDSXGR_EEPROMCTRL 0x0020
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#define YDSXGR_SPDIFINCTRL 0x0034
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#define YDSXGR_SPDIFINSTATUS 0x0038
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#define YDSXGR_DSPPROGRAMDL 0x0048
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#define YDSXGR_DLCNTRL 0x004C
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#define YDSXGR_GPIOININTFLAG 0x0050
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#define YDSXGR_GPIOININTENABLE 0x0052
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#define YDSXGR_GPIOINSTATUS 0x0054
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#define YDSXGR_GPIOOUTCTRL 0x0056
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#define YDSXGR_GPIOFUNCENABLE 0x0058
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#define YDSXGR_GPIOTYPECONFIG 0x005A
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#define YDSXGR_AC97CMDDATA 0x0060
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#define YDSXGR_AC97CMDADR 0x0062
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#define YDSXGR_PRISTATUSDATA 0x0064
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#define YDSXGR_PRISTATUSADR 0x0066
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#define YDSXGR_SECSTATUSDATA 0x0068
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#define YDSXGR_SECSTATUSADR 0x006A
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#define YDSXGR_SECCONFIG 0x0070
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#define YDSXGR_LEGACYOUTVOL 0x0080
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#define YDSXGR_LEGACYOUTVOLL 0x0080
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#define YDSXGR_LEGACYOUTVOLR 0x0082
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#define YDSXGR_NATIVEDACOUTVOL 0x0084
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#define YDSXGR_NATIVEDACOUTVOLL 0x0084
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#define YDSXGR_NATIVEDACOUTVOLR 0x0086
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#define YDSXGR_ZVOUTVOL 0x0088
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#define YDSXGR_ZVOUTVOLL 0x0088
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#define YDSXGR_ZVOUTVOLR 0x008A
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#define YDSXGR_SECADCOUTVOL 0x008C
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#define YDSXGR_SECADCOUTVOLL 0x008C
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#define YDSXGR_SECADCOUTVOLR 0x008E
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#define YDSXGR_PRIADCOUTVOL 0x0090
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#define YDSXGR_PRIADCOUTVOLL 0x0090
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#define YDSXGR_PRIADCOUTVOLR 0x0092
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#define YDSXGR_LEGACYLOOPVOL 0x0094
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#define YDSXGR_LEGACYLOOPVOLL 0x0094
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#define YDSXGR_LEGACYLOOPVOLR 0x0096
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#define YDSXGR_NATIVEDACLOOPVOL 0x0098
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#define YDSXGR_NATIVEDACLOOPVOLL 0x0098
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#define YDSXGR_NATIVEDACLOOPVOLR 0x009A
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#define YDSXGR_ZVLOOPVOL 0x009C
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#define YDSXGR_ZVLOOPVOLL 0x009E
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#define YDSXGR_ZVLOOPVOLR 0x009E
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#define YDSXGR_SECADCLOOPVOL 0x00A0
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#define YDSXGR_SECADCLOOPVOLL 0x00A0
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#define YDSXGR_SECADCLOOPVOLR 0x00A2
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#define YDSXGR_PRIADCLOOPVOL 0x00A4
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#define YDSXGR_PRIADCLOOPVOLL 0x00A4
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#define YDSXGR_PRIADCLOOPVOLR 0x00A6
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#define YDSXGR_NATIVEADCINVOL 0x00A8
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#define YDSXGR_NATIVEADCINVOLL 0x00A8
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#define YDSXGR_NATIVEADCINVOLR 0x00AA
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#define YDSXGR_NATIVEDACINVOL 0x00AC
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#define YDSXGR_NATIVEDACINVOLL 0x00AC
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#define YDSXGR_NATIVEDACINVOLR 0x00AE
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#define YDSXGR_BUF441OUTVOL 0x00B0
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#define YDSXGR_BUF441OUTVOLL 0x00B0
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#define YDSXGR_BUF441OUTVOLR 0x00B2
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#define YDSXGR_BUF441LOOPVOL 0x00B4
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#define YDSXGR_BUF441LOOPVOLL 0x00B4
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#define YDSXGR_BUF441LOOPVOLR 0x00B6
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#define YDSXGR_SPDIFOUTVOL 0x00B8
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#define YDSXGR_SPDIFOUTVOLL 0x00B8
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#define YDSXGR_SPDIFOUTVOLR 0x00BA
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#define YDSXGR_SPDIFLOOPVOL 0x00BC
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#define YDSXGR_SPDIFLOOPVOLL 0x00BC
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#define YDSXGR_SPDIFLOOPVOLR 0x00BE
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#define YDSXGR_ADCSLOTSR 0x00C0
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#define YDSXGR_RECSLOTSR 0x00C4
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#define YDSXGR_ADCFORMAT 0x00C8
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#define YDSXGR_RECFORMAT 0x00CC
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#define YDSXGR_P44SLOTSR 0x00D0
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#define YDSXGR_STATUS 0x0100
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#define YDSXGR_CTRLSELECT 0x0104
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#define YDSXGR_MODE 0x0108
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#define YDSXGR_SAMPLECOUNT 0x010C
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#define YDSXGR_NUMOFSAMPLES 0x0110
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#define YDSXGR_CONFIG 0x0114
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#define YDSXGR_PLAYCTRLSIZE 0x0140
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#define YDSXGR_RECCTRLSIZE 0x0144
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#define YDSXGR_EFFCTRLSIZE 0x0148
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#define YDSXGR_WORKSIZE 0x014C
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#define YDSXGR_MAPOFREC 0x0150
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#define YDSXGR_MAPOFEFFECT 0x0154
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#define YDSXGR_PLAYCTRLBASE 0x0158
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#define YDSXGR_RECCTRLBASE 0x015C
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#define YDSXGR_EFFCTRLBASE 0x0160
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#define YDSXGR_WORKBASE 0x0164
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#define YDSXGR_DSPINSTRAM 0x1000
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#define YDSXGR_CTRLINSTRAM 0x4000
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#define YDSXG_AC97READCMD 0x8000
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#define YDSXG_AC97WRITECMD 0x0000
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#define PCIR_DSXG_LEGACY 0x40
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#define PCIR_DSXG_ELEGACY 0x42
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#define PCIR_DSXG_CTRL 0x48
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#define PCIR_DSXG_PWRCTRL1 0x4a
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#define PCIR_DSXG_PWRCTRL2 0x4e
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#define PCIR_DSXG_FMBASE 0x60
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#define PCIR_DSXG_SBBASE 0x62
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#define PCIR_DSXG_MPU401BASE 0x64
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#define PCIR_DSXG_JOYBASE 0x66
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#define YDSXG_DSPLENGTH 0x0080
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#define YDSXG_CTRLLENGTH 0x3000
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#define YDSXG_DEFAULT_WORK_SIZE 0x0400
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#define YDSXG_PLAYBACK_VOICES 64
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#define YDSXG_CAPTURE_VOICES 2
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#define YDSXG_EFFECT_VOICES 5
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#define YMFPCI_LEGACY_SBEN (1 << 0) /* soundblaster enable */
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#define YMFPCI_LEGACY_FMEN (1 << 1) /* OPL3 enable */
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#define YMFPCI_LEGACY_JPEN (1 << 2) /* joystick enable */
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#define YMFPCI_LEGACY_MEN (1 << 3) /* MPU401 enable */
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#define YMFPCI_LEGACY_MIEN (1 << 4) /* MPU RX irq enable */
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#define YMFPCI_LEGACY_IOBITS (1 << 5) /* i/o bits range, 0 = 16bit, 1 =10bit */
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#define YMFPCI_LEGACY_SDMA (3 << 6) /* SB DMA select */
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#define YMFPCI_LEGACY_SBIRQ (7 << 8) /* SB IRQ select */
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#define YMFPCI_LEGACY_MPUIRQ (7 << 11) /* MPU IRQ select */
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#define YMFPCI_LEGACY_SIEN (1 << 14) /* serialized IRQ */
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#define YMFPCI_LEGACY_LAD (1 << 15) /* legacy audio disable */
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#define YMFPCI_LEGACY2_FMIO (3 << 0) /* OPL3 i/o address (724/740) */
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#define YMFPCI_LEGACY2_SBIO (3 << 2) /* SB i/o address (724/740) */
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#define YMFPCI_LEGACY2_MPUIO (3 << 4) /* MPU401 i/o address (724/740) */
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#define YMFPCI_LEGACY2_JSIO (3 << 6) /* joystick i/o address (724/740) */
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#define YMFPCI_LEGACY2_MAIM (1 << 8) /* MPU401 ack intr mask */
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#define YMFPCI_LEGACY2_SMOD (3 << 11) /* SB DMA mode */
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#define YMFPCI_LEGACY2_SBVER (3 << 13) /* SB version select */
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#define YMFPCI_LEGACY2_IMOD (1 << 15) /* legacy IRQ mode */
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/* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */
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#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
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#define SUPPORT_JOYSTICK
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#endif
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/*
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*
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*/
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typedef struct _snd_ymfpci_playback_bank {
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u32 format;
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u32 loop_default;
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u32 base; /* 32-bit address */
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u32 loop_start; /* 32-bit offset */
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u32 loop_end; /* 32-bit offset */
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u32 loop_frac; /* 8-bit fraction - loop_start */
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u32 delta_end; /* pitch delta end */
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u32 lpfK_end;
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u32 eg_gain_end;
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u32 left_gain_end;
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u32 right_gain_end;
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u32 eff1_gain_end;
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u32 eff2_gain_end;
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u32 eff3_gain_end;
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u32 lpfQ;
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u32 status;
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u32 num_of_frames;
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u32 loop_count;
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u32 start;
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u32 start_frac;
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u32 delta;
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u32 lpfK;
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u32 eg_gain;
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u32 left_gain;
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u32 right_gain;
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u32 eff1_gain;
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u32 eff2_gain;
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u32 eff3_gain;
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u32 lpfD1;
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u32 lpfD2;
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} snd_ymfpci_playback_bank_t;
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typedef struct _snd_ymfpci_capture_bank {
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u32 base; /* 32-bit address */
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u32 loop_end; /* 32-bit offset */
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u32 start; /* 32-bit offset */
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u32 num_of_loops; /* counter */
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} snd_ymfpci_capture_bank_t;
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typedef struct _snd_ymfpci_effect_bank {
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u32 base; /* 32-bit address */
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u32 loop_end; /* 32-bit offset */
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u32 start; /* 32-bit offset */
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u32 temp;
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} snd_ymfpci_effect_bank_t;
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typedef struct _snd_ymfpci_voice ymfpci_voice_t;
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typedef struct _snd_ymfpci_pcm ymfpci_pcm_t;
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typedef struct _snd_ymfpci ymfpci_t;
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typedef enum {
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YMFPCI_PCM,
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YMFPCI_SYNTH,
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YMFPCI_MIDI
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} ymfpci_voice_type_t;
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struct _snd_ymfpci_voice {
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ymfpci_t *chip;
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int number;
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unsigned int use: 1,
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pcm: 1,
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synth: 1,
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midi: 1;
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snd_ymfpci_playback_bank_t *bank;
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dma_addr_t bank_addr;
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void (*interrupt)(ymfpci_t *chip, ymfpci_voice_t *voice);
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ymfpci_pcm_t *ypcm;
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};
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typedef enum {
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PLAYBACK_VOICE,
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CAPTURE_REC,
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CAPTURE_AC97,
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EFFECT_DRY_LEFT,
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EFFECT_DRY_RIGHT,
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EFFECT_EFF1,
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EFFECT_EFF2,
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EFFECT_EFF3
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} snd_ymfpci_pcm_type_t;
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struct _snd_ymfpci_pcm {
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ymfpci_t *chip;
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snd_ymfpci_pcm_type_t type;
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snd_pcm_substream_t *substream;
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ymfpci_voice_t *voices[2]; /* playback only */
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unsigned int running: 1;
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unsigned int output_front: 1;
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unsigned int output_rear: 1;
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unsigned int update_pcm_vol;
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u32 period_size; /* cached from runtime->period_size */
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u32 buffer_size; /* cached from runtime->buffer_size */
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u32 period_pos;
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u32 last_pos;
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u32 capture_bank_number;
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u32 shift;
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};
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struct _snd_ymfpci {
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int irq;
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unsigned int device_id; /* PCI device ID */
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unsigned int rev; /* PCI revision */
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unsigned long reg_area_phys;
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void __iomem *reg_area_virt;
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struct resource *res_reg_area;
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struct resource *fm_res;
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struct resource *mpu_res;
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unsigned short old_legacy_ctrl;
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#ifdef SUPPORT_JOYSTICK
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struct gameport *gameport;
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#endif
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struct snd_dma_buffer work_ptr;
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unsigned int bank_size_playback;
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unsigned int bank_size_capture;
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unsigned int bank_size_effect;
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unsigned int work_size;
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void *bank_base_playback;
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void *bank_base_capture;
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void *bank_base_effect;
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void *work_base;
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dma_addr_t bank_base_playback_addr;
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dma_addr_t bank_base_capture_addr;
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dma_addr_t bank_base_effect_addr;
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dma_addr_t work_base_addr;
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struct snd_dma_buffer ac3_tmp_base;
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u32 *ctrl_playback;
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snd_ymfpci_playback_bank_t *bank_playback[YDSXG_PLAYBACK_VOICES][2];
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snd_ymfpci_capture_bank_t *bank_capture[YDSXG_CAPTURE_VOICES][2];
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snd_ymfpci_effect_bank_t *bank_effect[YDSXG_EFFECT_VOICES][2];
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int start_count;
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u32 active_bank;
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ymfpci_voice_t voices[64];
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ac97_bus_t *ac97_bus;
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ac97_t *ac97;
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snd_rawmidi_t *rawmidi;
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snd_timer_t *timer;
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struct pci_dev *pci;
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snd_card_t *card;
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snd_pcm_t *pcm;
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snd_pcm_t *pcm2;
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snd_pcm_t *pcm_spdif;
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snd_pcm_t *pcm_4ch;
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snd_pcm_substream_t *capture_substream[YDSXG_CAPTURE_VOICES];
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snd_pcm_substream_t *effect_substream[YDSXG_EFFECT_VOICES];
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snd_kcontrol_t *ctl_vol_recsrc;
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snd_kcontrol_t *ctl_vol_adcrec;
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snd_kcontrol_t *ctl_vol_spdifrec;
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unsigned short spdif_bits, spdif_pcm_bits;
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snd_kcontrol_t *spdif_pcm_ctl;
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int mode_dup4ch;
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int rear_opened;
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int spdif_opened;
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struct {
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u16 left;
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u16 right;
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snd_kcontrol_t *ctl;
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} pcm_mixer[32];
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spinlock_t reg_lock;
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spinlock_t voice_lock;
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wait_queue_head_t interrupt_sleep;
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atomic_t interrupt_sleep_count;
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snd_info_entry_t *proc_entry;
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#ifdef CONFIG_PM
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u32 *saved_regs;
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u32 saved_ydsxgr_mode;
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#endif
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};
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int snd_ymfpci_create(snd_card_t * card,
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struct pci_dev *pci,
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unsigned short old_legacy_ctrl,
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ymfpci_t ** rcodec);
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void snd_ymfpci_free_gameport(ymfpci_t *chip);
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int snd_ymfpci_pcm(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
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int snd_ymfpci_pcm2(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
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int snd_ymfpci_pcm_spdif(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
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int snd_ymfpci_pcm_4ch(ymfpci_t *chip, int device, snd_pcm_t **rpcm);
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int snd_ymfpci_mixer(ymfpci_t *chip, int rear_switch);
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int snd_ymfpci_timer(ymfpci_t *chip, int device);
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#endif /* __SOUND_YMFPCI_H */
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