2f01a1f588
wl12xx is a driver for TI wl1251 802.11 chipset designed for embedded devices, supporting both SDIO and SPI busses. Currently the driver supports only SPI. Adding support 1253 (the 5 GHz version) should be relatively easy. More information here: http://focus.ti.com/general/docs/wtbu/wtbuproductcontent.tsp?contentId=4711&navigationId=12494&templateId=6123 (Collapsed original sequence of pre-merge patches into single commit for initial merge. -- JWL) Signed-off-by: Kalle Valo <kalle.valo@nokia.com> Signed-off-by: Bob Copeland <me@bobcopeland.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
359 lines
9.7 KiB
C
359 lines
9.7 KiB
C
/*
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* This file is part of wl12xx
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*
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* Copyright (C) 2008 Nokia Corporation
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*
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* Contact: Kalle Valo <kalle.valo@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/crc7.h>
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#include <linux/spi/spi.h>
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#include "wl12xx.h"
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#include "wl12xx_80211.h"
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#include "reg.h"
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#include "spi.h"
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#include "ps.h"
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static int wl12xx_translate_reg_addr(struct wl12xx *wl, int addr)
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{
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/* If the address is lower than REGISTERS_BASE, it means that this is
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* a chip-specific register address, so look it up in the registers
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* table */
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if (addr < REGISTERS_BASE) {
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/* Make sure we don't go over the table */
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if (addr >= ACX_REG_TABLE_LEN) {
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wl12xx_error("address out of range (%d)", addr);
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return -EINVAL;
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}
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addr = wl->chip.acx_reg_table[addr];
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}
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return addr - wl->physical_reg_addr + wl->virtual_reg_addr;
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}
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static int wl12xx_translate_mem_addr(struct wl12xx *wl, int addr)
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{
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return addr - wl->physical_mem_addr + wl->virtual_mem_addr;
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}
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void wl12xx_spi_reset(struct wl12xx *wl)
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{
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u8 *cmd;
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struct spi_transfer t;
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struct spi_message m;
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cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
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if (!cmd) {
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wl12xx_error("could not allocate cmd for spi reset");
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return;
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}
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memset(&t, 0, sizeof(t));
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spi_message_init(&m);
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memset(cmd, 0xff, WSPI_INIT_CMD_LEN);
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t.tx_buf = cmd;
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t.len = WSPI_INIT_CMD_LEN;
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spi_message_add_tail(&t, &m);
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spi_sync(wl->spi, &m);
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wl12xx_dump(DEBUG_SPI, "spi reset -> ", cmd, WSPI_INIT_CMD_LEN);
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}
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void wl12xx_spi_init(struct wl12xx *wl)
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{
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u8 crc[WSPI_INIT_CMD_CRC_LEN], *cmd;
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struct spi_transfer t;
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struct spi_message m;
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cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
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if (!cmd) {
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wl12xx_error("could not allocate cmd for spi init");
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return;
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}
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memset(crc, 0, sizeof(crc));
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memset(&t, 0, sizeof(t));
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spi_message_init(&m);
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/*
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* Set WSPI_INIT_COMMAND
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* the data is being send from the MSB to LSB
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*/
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cmd[2] = 0xff;
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cmd[3] = 0xff;
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cmd[1] = WSPI_INIT_CMD_START | WSPI_INIT_CMD_TX;
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cmd[0] = 0;
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cmd[7] = 0;
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cmd[6] |= HW_ACCESS_WSPI_INIT_CMD_MASK << 3;
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cmd[6] |= HW_ACCESS_WSPI_FIXED_BUSY_LEN & WSPI_INIT_CMD_FIXEDBUSY_LEN;
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if (HW_ACCESS_WSPI_FIXED_BUSY_LEN == 0)
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cmd[5] |= WSPI_INIT_CMD_DIS_FIXEDBUSY;
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else
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cmd[5] |= WSPI_INIT_CMD_EN_FIXEDBUSY;
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cmd[5] |= WSPI_INIT_CMD_IOD | WSPI_INIT_CMD_IP | WSPI_INIT_CMD_CS
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| WSPI_INIT_CMD_WSPI | WSPI_INIT_CMD_WS;
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crc[0] = cmd[1];
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crc[1] = cmd[0];
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crc[2] = cmd[7];
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crc[3] = cmd[6];
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crc[4] = cmd[5];
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cmd[4] |= crc7(0, crc, WSPI_INIT_CMD_CRC_LEN) << 1;
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cmd[4] |= WSPI_INIT_CMD_END;
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t.tx_buf = cmd;
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t.len = WSPI_INIT_CMD_LEN;
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spi_message_add_tail(&t, &m);
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spi_sync(wl->spi, &m);
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wl12xx_dump(DEBUG_SPI, "spi init -> ", cmd, WSPI_INIT_CMD_LEN);
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}
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/* Set the SPI partitions to access the chip addresses
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*
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* There are two VIRTUAL (SPI) partitions (the memory partition and the
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* registers partition), which are mapped to two different areas of the
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* PHYSICAL (hardware) memory. This function also makes other checks to
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* ensure that the partitions are not overlapping. In the diagram below, the
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* memory partition comes before the register partition, but the opposite is
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* also supported.
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*
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* PHYSICAL address
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* space
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*
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* | |
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* ...+----+--> mem_start
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* VIRTUAL address ... | |
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* space ... | | [PART_0]
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* ... | |
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* 0x00000000 <--+----+... ...+----+--> mem_start + mem_size
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* | | ... | |
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* |MEM | ... | |
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* | | ... | |
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* part_size <--+----+... | | {unused area)
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* | | ... | |
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* |REG | ... | |
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* part_size | | ... | |
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* + <--+----+... ...+----+--> reg_start
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* reg_size ... | |
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* ... | | [PART_1]
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* ... | |
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* ...+----+--> reg_start + reg_size
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* | |
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*
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*/
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void wl12xx_set_partition(struct wl12xx *wl,
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u32 mem_start, u32 mem_size,
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u32 reg_start, u32 reg_size)
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{
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u8 tx_buf[sizeof(u32) + 2 * sizeof(struct wl12xx_partition)];
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struct wl12xx_partition *partition;
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struct spi_transfer t;
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struct spi_message m;
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u32 *cmd;
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size_t len;
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int addr;
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spi_message_init(&m);
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memset(&t, 0, sizeof(t));
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memset(tx_buf, 0, sizeof(tx_buf));
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cmd = (u32 *) tx_buf;
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partition = (struct wl12xx_partition *) (tx_buf + sizeof(u32));
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addr = HW_ACCESS_PART0_SIZE_ADDR;
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len = 2 * sizeof(struct wl12xx_partition);
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*cmd |= WSPI_CMD_WRITE;
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*cmd |= (len << WSPI_CMD_BYTE_LENGTH_OFFSET) & WSPI_CMD_BYTE_LENGTH;
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*cmd |= addr & WSPI_CMD_BYTE_ADDR;
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wl12xx_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
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mem_start, mem_size);
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wl12xx_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
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reg_start, reg_size);
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/* Make sure that the two partitions together don't exceed the
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* address range */
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if ((mem_size + reg_size) > HW_ACCESS_MEMORY_MAX_RANGE) {
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wl12xx_debug(DEBUG_SPI, "Total size exceeds maximum virtual"
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" address range. Truncating partition[0].");
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mem_size = HW_ACCESS_MEMORY_MAX_RANGE - reg_size;
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wl12xx_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
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mem_start, mem_size);
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wl12xx_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
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reg_start, reg_size);
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}
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if ((mem_start < reg_start) &&
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((mem_start + mem_size) > reg_start)) {
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/* Guarantee that the memory partition doesn't overlap the
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* registers partition */
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wl12xx_debug(DEBUG_SPI, "End of partition[0] is "
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"overlapping partition[1]. Adjusted.");
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mem_size = reg_start - mem_start;
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wl12xx_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
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mem_start, mem_size);
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wl12xx_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
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reg_start, reg_size);
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} else if ((reg_start < mem_start) &&
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((reg_start + reg_size) > mem_start)) {
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/* Guarantee that the register partition doesn't overlap the
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* memory partition */
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wl12xx_debug(DEBUG_SPI, "End of partition[1] is"
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" overlapping partition[0]. Adjusted.");
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reg_size = mem_start - reg_start;
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wl12xx_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
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mem_start, mem_size);
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wl12xx_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
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reg_start, reg_size);
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}
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partition[0].start = mem_start;
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partition[0].size = mem_size;
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partition[1].start = reg_start;
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partition[1].size = reg_size;
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wl->physical_mem_addr = mem_start;
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wl->physical_reg_addr = reg_start;
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wl->virtual_mem_addr = 0;
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wl->virtual_reg_addr = mem_size;
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t.tx_buf = tx_buf;
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t.len = sizeof(tx_buf);
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spi_message_add_tail(&t, &m);
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spi_sync(wl->spi, &m);
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}
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void wl12xx_spi_read(struct wl12xx *wl, int addr, void *buf,
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size_t len)
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{
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struct spi_transfer t[3];
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struct spi_message m;
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char busy_buf[TNETWIF_READ_OFFSET_BYTES];
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u32 cmd;
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cmd = 0;
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cmd |= WSPI_CMD_READ;
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cmd |= (len << WSPI_CMD_BYTE_LENGTH_OFFSET) & WSPI_CMD_BYTE_LENGTH;
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cmd |= addr & WSPI_CMD_BYTE_ADDR;
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].tx_buf = &cmd;
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t[0].len = 4;
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spi_message_add_tail(&t[0], &m);
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/* Busy and non busy words read */
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t[1].rx_buf = busy_buf;
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t[1].len = TNETWIF_READ_OFFSET_BYTES;
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spi_message_add_tail(&t[1], &m);
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t[2].rx_buf = buf;
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t[2].len = len;
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spi_message_add_tail(&t[2], &m);
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spi_sync(wl->spi, &m);
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/* FIXME: check busy words */
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wl12xx_dump(DEBUG_SPI, "spi_read cmd -> ", &cmd, sizeof(cmd));
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wl12xx_dump(DEBUG_SPI, "spi_read buf <- ", buf, len);
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}
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void wl12xx_spi_write(struct wl12xx *wl, int addr, void *buf,
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size_t len)
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{
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struct spi_transfer t[2];
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struct spi_message m;
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u32 cmd;
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cmd = 0;
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cmd |= WSPI_CMD_WRITE;
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cmd |= (len << WSPI_CMD_BYTE_LENGTH_OFFSET) & WSPI_CMD_BYTE_LENGTH;
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cmd |= addr & WSPI_CMD_BYTE_ADDR;
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].tx_buf = &cmd;
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t[0].len = sizeof(cmd);
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spi_message_add_tail(&t[0], &m);
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t[1].tx_buf = buf;
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t[1].len = len;
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spi_message_add_tail(&t[1], &m);
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spi_sync(wl->spi, &m);
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wl12xx_dump(DEBUG_SPI, "spi_write cmd -> ", &cmd, sizeof(cmd));
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wl12xx_dump(DEBUG_SPI, "spi_write buf -> ", buf, len);
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}
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void wl12xx_spi_mem_read(struct wl12xx *wl, int addr, void *buf,
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size_t len)
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{
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int physical;
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physical = wl12xx_translate_mem_addr(wl, addr);
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wl12xx_spi_read(wl, physical, buf, len);
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}
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void wl12xx_spi_mem_write(struct wl12xx *wl, int addr, void *buf,
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size_t len)
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{
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int physical;
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physical = wl12xx_translate_mem_addr(wl, addr);
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wl12xx_spi_write(wl, physical, buf, len);
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}
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u32 wl12xx_mem_read32(struct wl12xx *wl, int addr)
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{
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return wl12xx_read32(wl, wl12xx_translate_mem_addr(wl, addr));
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}
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void wl12xx_mem_write32(struct wl12xx *wl, int addr, u32 val)
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{
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wl12xx_write32(wl, wl12xx_translate_mem_addr(wl, addr), val);
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}
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u32 wl12xx_reg_read32(struct wl12xx *wl, int addr)
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{
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return wl12xx_read32(wl, wl12xx_translate_reg_addr(wl, addr));
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}
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void wl12xx_reg_write32(struct wl12xx *wl, int addr, u32 val)
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{
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wl12xx_write32(wl, wl12xx_translate_reg_addr(wl, addr), val);
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}
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